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1. 发明授权

US07709776B2 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
标题翻译：具有光学器件的微电子成像器和制造这种微电子成像器的方法
公开(公告)号：US07709776B2
公开(公告)日：2010-05-04
申请号：US12390195
申请日：2009-02-20
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L27/00 , H01L31/0232
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
摘要翻译：微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。微电子成像器组件还包括相对于成像管芯叠加的光学支架。光学支撑件可以直接在基板上或衬底上的盖上。单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

2. 发明授权

US07645635B2 Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages 有权
标题翻译：用于制造图像传感器封装等的框架结构和半导体附着工艺以及所产生的封装
公开(公告)号：US07645635B2
公开(公告)日：2010-01-12
申请号：US10919604
申请日：2004-08-16
申请人： Alan G. Wood , Kyle K. Kirby , Warren M. Farnworth , Salman Akram
发明人： Alan G. Wood , Kyle K. Kirby , Warren M. Farnworth , Salman Akram
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , B33Y80/00 , H01L27/14625 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used for the packages.
摘要翻译：诸如图像传感器封装的半导体封装以及制造方法。框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口，然后安装其他包装组件。在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。各种外部连接方法可用于包装。

3. 发明授权

US07598167B2 Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures 有权
标题翻译：在半导体衬底中形成通孔的方法，而不损坏其有效区域和结果
公开(公告)号：US07598167B2
公开(公告)日：2009-10-06
申请号：US11140402
申请日：2005-05-27
申请人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a semiconductor substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying semiconductor substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by ablation or drilling from the back surface of the semiconductor substrate followed by dry etching to complete the through via and expose the underside of the conductive element.
摘要翻译：公开了在半导体衬底中形成贯通孔的方法和所得到的结构。在一个实施例中，通孔可以通过在其上的导电元件和导电元件下面的半导体衬底的一部分从活性表面形成部分通孔而形成通孔。然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。在另一个实施例中，部分通孔可以通过激光烧蚀或从半导体衬底的背面钻孔到其中的预定距离来形成。通孔可以通过形成延伸穿过导电元件和下面的半导体衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。在另一个实施例中，可以首先通过从半导体衬底的后表面进行烧蚀或钻孔形成部分通孔，然后进行干法蚀刻以完成通孔并暴露导电元件的下侧。

4. 发明申请

US20090155949A1 MICROELECTRONIC IMAGERS WITH OPTICAL DEVICES AND METHODS OF MANUFACTURING SUCH MICROELECTRONIC IMAGERS 有权
标题翻译：具有光学器件的微电子成像器和制造这种微电子成像器的方法
公开(公告)号：US20090155949A1
公开(公告)日：2009-06-18
申请号：US12390195
申请日：2009-02-20
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L31/0232
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
摘要翻译：微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。微电子成像器组件还包括相对于成像管芯叠加的光学支架。光学支撑件可以直接在基板上或衬底上的盖上。单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

5. 发明授权

US07250780B2 Probe card for semiconductor wafers having mounting plate and socket 失效
标题翻译：带安装板和插座的半导体晶圆探头卡
公开(公告)号：US07250780B2
公开(公告)日：2007-07-31
申请号：US10742729
申请日：2003-12-19
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

6. 发明授权

US06980014B2 Interposer and methods for fabricating same 失效
标题翻译：插件及其制造方法
公开(公告)号：US06980014B2
公开(公告)日：2005-12-27
申请号：US10379221
申请日：2003-03-04
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , H05K1/11 , H05K1/14 , H05K3/34 , G01R31/02
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with a substrate. The fence may include edges that are configured to progressively align a semiconductor device with the substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，包括接收半导体器件（例如倒装芯片型半导体器件）和衬底的栅栏。栅栏可以包括被配置为逐渐地将半导体器件与衬底对准的边缘。栅栏还可以包括一个或多个侧向凹入的区域，以便于半导体器件与衬底的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备，并且有助于识别材料在其上和周围的位置和取向施加在一个或多个层中以形成栅栏。因此，基板不需要精确地机械对准。

7. 发明授权

US06548392B2 Methods of a high density flip chip memory arrays 有权
标题翻译：高密度倒装芯片存储阵列的方法
公开(公告)号：US06548392B2
公开(公告)日：2003-04-15
申请号：US09398337
申请日：1999-09-17
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2144
CPC分类号： H01L24/81 , H01L23/552 , H01L23/556 , H01L27/10897 , H01L2224/05001 , H01L2224/05027 , H01L2224/05572 , H01L2224/13111 , H01L2224/1319 , H01L2224/16 , H01L2224/274 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： A low alpha emissivity-induced error solder bump, flip-chip integrated circuit device. The device includes a semiconductor die having an active surface and a bond pad array disposed about the active surface of the die. The active surface of the die includes logic circuits adjacent memory cell arrays. Each of the bond pads directly overlays a logic circuit, to which they may be connected. The present invention also includes methods for designing and fabricating the invented devices and connecting them to a carrier substrate.
摘要翻译：低α辐射率引起的误差焊料凸块，倒装芯片集成电路器件。该器件包括具有活动表面的半导体管芯和围绕管芯的有效表面设置的接合焊盘阵列。芯片的有源表面包括与存储单元阵列相邻的逻辑电路。每个接合焊盘直接覆盖它们可以连接到的逻辑电路。本发明还包括用于设计和制造本发明的装置并将其连接到载体基板的方法。

8. 发明授权

US06392429B1 Temporary semiconductor package having dense array external contacts 失效
标题翻译：具有密集阵列外部触点的临时半导体封装
公开(公告)号：US06392429B1
公开(公告)日：2002-05-21
申请号：US09594748
申请日：2000-06-14
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Salman Akram
IPC分类号： G01R3102
CPC分类号： H01L23/49838 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/0735 , G01R3/00 , G01R31/2863 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/80 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2225/06562 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/05599
摘要： A temporary package for a semiconductor die is provided. The temporary package has an outline and external contact configuration that are the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. The package includes a base, an interconnect and a force applying mechanism. The package base includes external contacts formed in a dense array, such as a land grid array (LGA), a pin grid array (PGA), a bumped grid array (BGA) or a perimeter array. The package base can be formed of ceramic or plastic with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip formation process.
摘要翻译：提供了一种用于半导体管芯的临时封装。临时包装具有与常规塑料或陶瓷半导体封装相同的轮廓和外部接触构造。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。该包装包括底座，互连和力施加机构。封装基座包括形成在密集阵列中的外部触头，例如焊盘格栅阵列（LGA），引脚格栅阵列（PGA），凸起栅格阵列（BGA）或周边阵列。封装基底可以由具有内部导电线的陶瓷或塑料形成，使用陶瓷层压工艺，3-D成型工艺或Cerdip形成工艺。

9. 发明授权

US06313651B1 Carrier and system for testing bumped semiconductor components 失效
标题翻译：用于测试碰撞半导体元件的载体和系统
公开(公告)号：US06313651B1
公开(公告)日：2001-11-06
申请号：US09322724
申请日：1999-05-28
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , H01L2224/0401 , H01L2224/05552 , H01L2224/48091 , H01L2224/81385 , H01L2924/01021 , H01L2924/01087 , H01L2924/09701 , H01L2924/10155 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
摘要翻译：提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。载体包括基底，互连和力施加机构。互连包括适于电接触接触凸块的接触构件的图案。互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。或者，互连可以是直接结合到载体的基底的多层带。除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。载体还可以包括配置成将部件与互连对准的对准部件。该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

10. 发明授权

US06287942B1 Hermetic chip and method of manufacture 有权
标题翻译：密封芯片和制造方法
公开(公告)号：US06287942B1
公开(公告)日：2001-09-11
申请号：US09518293
申请日：2000-03-03
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21301
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process the fully hermetic sealing of both sides and the edges of the semiconductor chip out the use of a separate package.
摘要翻译：一种完全密封的半导体芯片及其制造方法。本发明的半导体芯片通过使用适用于其上的合适的涂层（例如玻璃）在其两侧及其边缘上完全气密密封，以防止半导体芯片的环境攻击。本发明的完全密封的半导体芯片不需要使用用于芯片的气密密封的单独封装，从而减小这种芯片的尺寸。本发明的半导体芯片的制造方法提供了使用单独的封装完全密封半导体芯片的两侧和边缘的简单工艺。

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