专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20090232384A1 Mask Making Decision for Manufacturing (DFM) on Mask Quality Control 有权
标题翻译：面罩制造决策（DFM）面膜质量控制
公开(公告)号：US20090232384A1
公开(公告)日：2009-09-17
申请号：US12048043
申请日：2008-03-13
申请人： Chih-Chiang Tu , Chien-Chao Huang
发明人： Chih-Chiang Tu , Chien-Chao Huang
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.
摘要翻译：本公开提供了一种制造掩模的方法。该方法包括将多个模式特征分配给不同的数据类型; 在掩模上写入多个图案特征; 根据分配的数据类型检查具有不同检查灵敏度的多个图案特征; 以及根据所述多个图案特征的检查来修复所述掩模上的所述多个图案特征。

92. 发明授权

US07547605B2 Microelectronic device and a method for its manufacture 有权
标题翻译：微电子器件及其制造方法
公开(公告)号：US07547605B2
公开(公告)日：2009-06-16
申请号：US10994841
申请日：2004-11-22
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659
摘要： Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of the semiconductor substrate layer. A semiconductor layer is then formed in the openings directly upon the exposed portions of the semiconductor substrate layer using a second material different from the first material (e.g., silicon germanium or silicon). In other examples, multiple semiconductor layers may be formed using alternating materials.
摘要翻译：提供一种微电子器件及其制造方法。在一个示例中，该方法包括提供具有第一材料（例如硅或硅锗）的半导体衬底层。绝缘层形成在半导体衬底层上，多个开口露出半导体衬底层表面的部分。然后使用不同于第一材料（例如硅锗或硅）的第二材料在半导体衬底层的暴露部分上直接在开口中的开口中形成半导体层。在其他示例中，可以使用交替材料形成多个半导体层。

93. 发明授权

US07444199B2 Method for preparing mask and wafer data files 有权
标题翻译：掩模和晶圆数据文件的制作方法
公开(公告)号：US07444199B2
公开(公告)日：2008-10-28
申请号：US11626218
申请日：2007-01-23
申请人： Hsin-Ying Lee , Chien-Chao Huang , Chih-Chiang Tu
发明人： Hsin-Ying Lee , Chien-Chao Huang , Chih-Chiang Tu
IPC分类号： G06F19/00 , G06F17/50 , G05B19/42
CPC分类号： G03F1/68 , Y10S707/99945 , Y10S707/99948
摘要： A method for converting a data file into a writer file for a mask writer is provided. A plurality of sub-files is created from the data file. The plurality of sub-files is transferred to the mask writer. A plurality of writer files is created from the plurality of sub-files at the mask writer. The transferring the plurality of sub-files to the mask writer, creating a plurality of writer files from the plurality of sub-files at the mask writer, and checking the plurality of transferred sub-files at the mask writer are executed in parallel in a single process.
摘要翻译：提供了一种用于将数据文件转换成用于掩码写入器的写入器文件的方法。从数据文件创建多个子文件。多个子文件被传送到掩码写入器。在掩码写入器处从多个子文件创建多个写入器文件。将多个子文件传送到掩码写入器，在掩码写入器处从多个子文件创建多个写入器文件，并且在掩码写入器处检查多个传送的子文件，并行执行单一过程。

94. 发明申请

US20080263501A1 System, Method, and Computer-Readable Medium for Performing Data Preparation for a Mask Design 有权
标题翻译：用于进行掩模设计数据准备的系统，方法和计算机可读介质
公开(公告)号：US20080263501A1
公开(公告)日：2008-10-23
申请号：US11738844
申请日：2007-04-23
申请人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
发明人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed
摘要翻译：提供了一种用于执行数据准备的方法，计算机可读介质和系统。接收集成电路设计，并且调用多个预光学邻近校正处理，使得并行地执行多个预光学邻近校正处理。响应于多个预光学邻近校正处理中的每一个已经完成的确定来调用光学邻近校正处理。响应于光学邻近校正处理已经完成的确定，调用后光学邻近校正处理

95. 发明申请

US20070132035A1 Transistor mobility improvement by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来提高晶体管的迁移率
公开(公告)号：US20070132035A1
公开(公告)日：2007-06-14
申请号：US11702399
申请日：2007-02-05
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving the carrier mobility of a transistor is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. After the step of forming the silicide layer, a recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI causes the removal of the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain region and the dielectric. The CESL applies a desired stress to the channel region. Trench liners may optionally be formed to provide a stress to the channel region. A trench spacer may optionally be formed in the STI recess.
摘要翻译：提出了一种提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。在形成硅化物层的步骤之后，通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI导致STI材料去除施加到沟道区域的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可以可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成沟槽间隔物。

96. 发明授权

US07202122B2 Cobalt silicidation process for substrates with a silicon—germanium layer 有权
标题翻译：具有硅 - 锗层的衬底的钴硅化工艺
公开(公告)号：US07202122B2
公开(公告)日：2007-04-10
申请号：US10710012
申请日：2004-06-11
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/1054 , H01L29/665 , H01L29/66545 , Y10S438/933
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
摘要翻译：一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

97. 发明授权

US07190036B2 Transistor mobility improvement by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来提高晶体管的迁移率
公开(公告)号：US07190036B2
公开(公告)日：2007-03-13
申请号：US11004690
申请日：2004-12-03
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/76 , H01L29/76 , H01L29/97 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.
摘要翻译：提出了一种通过通过凹槽浅沟槽隔离来调节应力来提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI消除由STI材料施加到沟道区的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成间隔件。

98. 发明申请

US20070012905A1 Novel phase change random access memory 有权
标题翻译：新型相变随机存取存储器
公开(公告)号：US20070012905A1
公开(公告)日：2007-01-18
申请号：US11180430
申请日：2005-07-13
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective coating (ARC) film on the bottom electrode film, patterning and etching the ARC film and the bottom electrode film to form a bottom electrode comprising a side edge, and forming a phase change material portion on the ARC film and the bottom insulating layer, wherein the phase change material portion physically contacts the side edge of the bottom electrode. The method further includes forming a top electrode on the phase change material portion, and forming a top electrode contact on the top electrode.
摘要翻译：提供了具有减小的相变容积和较低驱动电流的相变存储器件及其形成方法。该方法包括形成底部绝缘层，该底部绝缘层包括底部电极触点，在底部电极触点上形成底部电极膜，在底部电极膜上形成抗反射涂层（ARC）膜，对ARC膜和底部形成包括侧边缘的底部电极，并且在所述ARC膜和所述底部绝缘层上形成相变材料部分，其中所述相变材料部分物理接触所述底部电极的侧边缘。该方法还包括在相变材料部分上形成顶部电极，以及在顶部电极上形成顶部电极接触。

99. 发明申请

US20060121688A1 Transistor mobility by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来实现晶体管迁移
公开(公告)号：US20060121688A1
公开(公告)日：2006-06-08
申请号：US11004690
申请日：2004-12-03
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.
摘要翻译：提出了一种通过通过凹槽浅沟槽隔离来调节应力来提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI消除由STI材料施加到沟道区的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成间隔件。

100. 发明申请

US20060110887A1 Microelectronic device and a method for its manufacture 有权
公开(公告)号：US20060110887A1
公开(公告)日：2006-05-25
申请号：US10994841
申请日：2004-11-22
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659
摘要： Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of the semiconductor substrate layer. A semiconductor layer is then formed in the openings directly upon the exposed portions of the semiconductor substrate layer using a second material different from the first material (e.g., silicon germanium or silicon). In other examples, multiple semiconductor layers may be formed using alternating materials.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式