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1. 发明申请

US20060205164A1 Method of forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US20060205164A1
公开(公告)日：2006-09-14
申请号：US11076707
申请日：2005-03-10
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L21/8234
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. Transistors are then formed in close proximity to the trenches and may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：用于隔离沟槽的方法和系统包括在半导体衬底中形成隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境退火以回流沟槽的边缘，从而使边缘变成圆形和悬垂的沟槽。填充材料可以是电介质。晶体管然后形成在沟槽附近，并且可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源/漏区。

2. 发明申请

US20070235835A1 Shallow trench isolation structure for semiconductor device 有权
标题翻译：用于半导体器件的浅沟槽隔离结构
公开(公告)号：US20070235835A1
公开(公告)日：2007-10-11
申请号：US11809519
申请日：2007-05-31
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：半导体器件提供与隔离沟槽相邻的晶体管。该器件可以通过在半导体衬底中产生隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境进行退火以使沟槽的边缘回流，从而使边缘变圆; 突出沟槽。填充材料可以是电介质。然后形成在靠近沟槽的晶体管可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源极/漏极区域。

3. 发明授权

US07745904B2 Shallow trench isolation structure for semiconductor device 有权
标题翻译：用于半导体器件的浅沟槽隔离结构
公开(公告)号：US07745904B2
公开(公告)日：2010-06-29
申请号：US11809519
申请日：2007-05-31
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：半导体器件提供与隔离沟槽相邻的晶体管。该器件可以通过在半导体衬底中产生隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境进行退火以使沟槽的边缘回流，从而使边缘变圆; 突出沟槽。填充材料可以是电介质。然后形成在靠近沟槽的晶体管可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源极/漏极区域。

4. 发明授权

US07465620B2 Transistor mobility improvement by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来提高晶体管的迁移率
公开(公告)号：US07465620B2
公开(公告)日：2008-12-16
申请号：US11702399
申请日：2007-02-05
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/44
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving the carrier mobility of a transistor is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. After the step of forming the silicide layer, a recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI causes the removal of the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain region and the dielectric. The CESL applies a desired stress to the channel region. Trench liners may optionally be formed to provide a stress to the channel region. A trench spacer may optionally be formed in the STI recess.
摘要翻译：提出了一种提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。在形成硅化物层的步骤之后，通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI导致STI材料去除施加到沟道区域的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可以可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成沟槽间隔物。

5. 发明授权

US07238564B2 Method of forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US07238564B2
公开(公告)日：2007-07-03
申请号：US11076707
申请日：2005-03-10
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/8238
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. Transistors are then formed in close proximity to the trenches and may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：用于隔离沟槽的方法和系统包括在半导体衬底中形成隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境退火以回流沟槽的边缘，从而使边缘变成圆形和悬垂的沟槽。填充材料可以是电介质。晶体管然后形成在沟槽附近，并且可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源/漏区。

6. 发明申请

US20070132035A1 Transistor mobility improvement by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来提高晶体管的迁移率
公开(公告)号：US20070132035A1
公开(公告)日：2007-06-14
申请号：US11702399
申请日：2007-02-05
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving the carrier mobility of a transistor is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. After the step of forming the silicide layer, a recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI causes the removal of the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain region and the dielectric. The CESL applies a desired stress to the channel region. Trench liners may optionally be formed to provide a stress to the channel region. A trench spacer may optionally be formed in the STI recess.
摘要翻译：提出了一种提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。在形成硅化物层的步骤之后，通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI导致STI材料去除施加到沟道区域的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可以可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成沟槽间隔物。

7. 发明授权

US07190036B2 Transistor mobility improvement by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来提高晶体管的迁移率
公开(公告)号：US07190036B2
公开(公告)日：2007-03-13
申请号：US11004690
申请日：2004-12-03
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/76 , H01L29/76 , H01L29/97 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.
摘要翻译：提出了一种通过通过凹槽浅沟槽隔离来调节应力来提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI消除由STI材料施加到沟道区的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成间隔件。

8. 发明申请

US20060121688A1 Transistor mobility by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来实现晶体管迁移
公开(公告)号：US20060121688A1
公开(公告)日：2006-06-08
申请号：US11004690
申请日：2004-12-03
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.
摘要翻译：提出了一种通过通过凹槽浅沟槽隔离来调节应力来提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI消除由STI材料施加到沟道区的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成间隔件。

9. 发明申请

US20050233552A1 Strained channel on insulator device 失效
公开(公告)号：US20050233552A1
公开(公告)日：2005-10-20
申请号：US11083537
申请日：2005-03-18
申请人： Chung-Hu Ke , Chao-Hsiung Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ke , Chao-Hsiung Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/00 , H01L21/30 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/02 , H01L29/72 , H01L29/772
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/7848
摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

10. 发明申请

US20050116360A1 Complementary field-effect transistors and methods of manufacture 审中-公开
标题翻译：互补场效应晶体管及其制造方法
公开(公告)号：US20050116360A1
公开(公告)日：2005-06-02
申请号：US10896270
申请日：2004-07-21
申请人： Chien-Chao Huang , Fu-Liang Yang , Mickey Ken , Chenming Hu , Chung-Hu Ge , Wen-Chin Lee , Chih-Hsin Ko
发明人： Chien-Chao Huang , Fu-Liang Yang , Mickey Ken , Chenming Hu , Chung-Hu Ge , Wen-Chin Lee , Chih-Hsin Ko
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L31/0328
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.
摘要翻译：提供互补的FET和制造方法。互补FET使用具有<100>晶体取向的表面层的衬底。通过硅化源极/漏极区域，拉伸应力膜，浅沟槽隔离层，层间电介质等添加了提高NMOS FET的性能的拉伸应力。

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