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1. 发明申请

US20080111825A1 PIXEL CACHE FOR 3D GRAPHICS CIRCUITRY 有权
标题翻译：用于3D图形电路的PIXEL CACHE
公开(公告)号：US20080111825A1
公开(公告)日：2008-05-15
申请号：US11621052
申请日：2007-01-08
申请人： William Torzewski , Chun Yu , Alexei V. Bourd
发明人： William Torzewski , Chun Yu , Alexei V. Bourd
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06F12/0875 , G06F12/127
摘要： Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.
摘要翻译：提供了包括设备存储器，硬件实体，子图像单元值高速缓存和高速缓存写入操作符的装置。至少一些硬件实体执行涉及对设备存储器的访问和使用的动作。硬件实体包括用于处理来自原始对象的3D图像的3D图形电路，用于准备显示。高速缓存与设备存储器分离，并被提供以保存数据，包括缓冲的子图像单元值。高速缓存连接到3D图形电路，使得3D图形电路的像素处理部分访问高速缓存中缓冲的子图像单元值，代替直接访问设备存储器中的子图像单元值的像素处理部分。写操作符将缓冲的子图像单元格值在优先级方案的方向下写入设备存储器。优先级方案保留在与一个或多个原始对象相邻的缓存边界单元格值中。

2. 发明授权

US07737985B2 Pixel cache for 3D graphics circuitry 有权
标题翻译：用于3D图形电路的像素缓存
公开(公告)号：US07737985B2
公开(公告)日：2010-06-15
申请号：US11621052
申请日：2007-01-08
申请人： William Torzewski , Chun Yu , Alexei V. Bourd
发明人： William Torzewski , Chun Yu , Alexei V. Bourd
IPC分类号： G09G5/36 , G06T15/30 , G06T17/20
CPC分类号： G06T1/60 , G06F12/0875 , G06F12/127
摘要： Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.
摘要翻译：提供了包括设备存储器，硬件实体，子图像单元值高速缓存和高速缓存写入操作符的装置。至少一些硬件实体执行涉及对设备存储器的访问和使用的动作。硬件实体包括用于处理来自原始对象的3D图像的3D图形电路，用于准备显示。高速缓存与设备存储器分离，并被提供以保存数据，包括缓冲的子图像单元值。高速缓存连接到3D图形电路，使得3D图形电路的像素处理部分访问高速缓存中缓冲的子图像单元值，代替直接访问设备存储器中的子图像单元值的像素处理部分。写操作符将缓冲的子图像单元格值在优先级方案的方向下写入设备存储器。优先级方案保留在与一个或多个原始对象相邻的缓存边界单元格值中。

3. 发明授权

US08884972B2 Graphics processor with arithmetic and elementary function units 有权
标题翻译：具有算术和基本功能单元的图形处理器
公开(公告)号：US08884972B2
公开(公告)日：2014-11-11
申请号：US11441696
申请日：2006-05-25
申请人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
发明人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
IPC分类号： G06F15/16 , G06F15/00 , G06T1/00 , G06F9/38 , G06F9/30
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

4. 发明申请

US20070273698A1 Graphics processor with arithmetic and elementary function units 有权
标题翻译：具有算术和基本功能单元的图形处理器
公开(公告)号：US20070273698A1
公开(公告)日：2007-11-29
申请号：US11441696
申请日：2006-05-25
申请人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
发明人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

5. 发明授权

US09804995B2 Computational resource pipelining in general purpose graphics processing unit 有权
公开(公告)号：US09804995B2
公开(公告)日：2017-10-31
申请号：US13007333
申请日：2011-01-14
申请人： Alexei V. Bourd , Andrew Gruber , Aleksandra L. Krstic , Robert J. Simpson , Colin Sharp , Chun Yu
发明人： Alexei V. Bourd , Andrew Gruber , Aleksandra L. Krstic , Robert J. Simpson , Colin Sharp , Chun Yu
IPC分类号： G06F15/00 , G06F15/76 , G06F15/173
CPC分类号： G06F15/17325
摘要： This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

6. 发明授权

US08355028B2 Scheme for varying packing and linking in graphics systems 有权
标题翻译：在图形系统中改变包装和链接的方案
公开(公告)号：US08355028B2
公开(公告)日：2013-01-15
申请号：US11830667
申请日：2007-07-30
申请人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

7. 发明申请

US20120185671A1 COMPUTATIONAL RESOURCE PIPELINING IN GENERAL PURPOSE GRAPHICS PROCESSING UNIT 有权
标题翻译：一般用途图形处理单元的计算资源管理
公开(公告)号：US20120185671A1
公开(公告)日：2012-07-19
申请号：US13007333
申请日：2011-01-14
申请人： Alexei V. Bourd , Andrew Gruber , Aleksandra L. Krstic , Robert J. Simpson , Colin Sharp , Chun Yu
发明人： Alexei V. Bourd , Andrew Gruber , Aleksandra L. Krstic , Robert J. Simpson , Colin Sharp , Chun Yu
IPC分类号： G06F9/38
CPC分类号： G06F15/17325
摘要： This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.
摘要翻译：本公开描述了用于利用并行处理单元来扩展通用图形处理单元（GPGPU）的架构以允许基于流水线的应用的有效处理的技术。这些技术包括配置连接到作为处理流水线的阶段的并行处理单元的本地存储器缓冲器，以保持用于在并行处理单元之间传送的数据。本地存储缓冲器允许并行处理单元之间的片上，低功耗，直接数据传输。本地存储器缓冲器可以包括基于硬件的数据流控制机制，以使得能够在并行处理单元之间传送数据。以这种方式，数据可以经由本地存储器缓冲器直接从一个并行处理单元传递到处理流水线中的下一个并行处理单元，实际上将并行处理单元转换成一系列流水线级。

8. 发明授权

US07944442B2 Graphics system employing shape buffer 有权
标题翻译：图形系统采用形状缓冲
公开(公告)号：US07944442B2
公开(公告)日：2011-05-17
申请号：US11609762
申请日：2006-12-12
申请人： Angus M. Dorbie , Alexei V. Bourd , Chun Yu
发明人： Angus M. Dorbie , Alexei V. Bourd , Chun Yu
IPC分类号： G06T15/40
CPC分类号： G06T11/40 , G06T2210/12
摘要： The system includes a shape buffer manager configured to store coverage data in the shape buffer. The coverage data indicates whether each mask pixel is a covered pixel or an uncovered pixel. A mask pixel is a covered pixel when a shape to be rendered on a screen covers the mask pixel such that one or more coverage criteria is satisfied and is an uncovered pixel when the shape does not cover the mask pixel such that the one or more coverage criteria are satisfied. A bounds primitive rasterizer is configured to rasterize a bounds primitive that bounds the shape. The bounds primitive is rasterized into primitive pixels that each corresponds to one of the mask pixels. A pixel screener is configured to employ the coverage data from the shape buffer to screen the primitive pixels into retained pixels and discarded pixels. The retained pixels each corresponds to a mask pixel that the coverage data indicates is a covered pixel and the discarded pixels each correspond to a mask pixels that the coverage data indicates is an uncovered pixel. The system also includes an attribute generator configured to generate pixel attributes for the retained primitive pixels and also configured not to generate pixel attributes for the discarded primitive pixels.
摘要翻译：该系统包括形状缓冲器管理器，其被配置为将覆盖数据存储在形状缓冲器中。覆盖数据指示每个掩模像素是被覆盖像素还是未覆盖像素。当要在屏幕上呈现的形状覆盖掩模像素使得满足一个或多个覆盖准则并且当形状不覆盖掩模像素时是未被覆盖的像素，使得一个或多个覆盖标准满足。边界原始光栅化器被配置为光栅化限制形状的边界原语。边界原语被光栅化为原始像素，每个像素对应于一个掩码像素。像素筛选器被配置为使用来自形状缓冲器的覆盖数据来将原始像素屏蔽到保留的像素和丢弃的像素中。保留像素分别对应于覆盖数据指示为被覆盖像素的掩码像素，并且丢弃的像素各自对应于覆盖数据指示的掩模像素是未覆盖的像素。该系统还包括属性生成器，其被配置为生成被保留的原始像素的像素属性，并且还被配置为不为所丢弃的原始像素生成像素属性。

9. 发明申请

US20090033672A1 SCHEME FOR VARYING PACKING AND LINKING IN GRAPHICS SYSTEMS 有权
标题翻译：在图形系统中改变包装和连接的方案
公开(公告)号：US20090033672A1
公开(公告)日：2009-02-05
申请号：US11830667
申请日：2007-07-30
申请人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

10. 发明申请

US20080122866A1 GRAPHICS SYSTEM EMPLOYING SHAPE BUFFER 有权
标题翻译：图形系统采用形状缓冲
公开(公告)号：US20080122866A1
公开(公告)日：2008-05-29
申请号：US11609762
申请日：2006-12-12
申请人： Angus M. Dorbie , Alexei V. Bourd , Chun Yu
发明人： Angus M. Dorbie , Alexei V. Bourd , Chun Yu
IPC分类号： G09G5/00
CPC分类号： G06T11/40 , G06T2210/12
摘要： The system includes a shape buffer manager configured to store coverage data in the shape buffer. The coverage data indicates whether each mask pixel is a covered pixel or an uncovered pixel. A mask pixel is a covered pixel when a shape to be rendered on a screen covers the mask pixel such that one or more coverage criteria is satisfied and is an uncovered pixel when the shape does not cover the mask pixel such that the one or more coverage criteria are satisfied. A bounds primitive rasterizer is configured to rasterize a bounds primitive that bounds the shape. The bounds primitive is rasterized into primitive pixels that each corresponds to one of the mask pixels. A pixel screener is configured to employ the coverage data from the shape buffer to screen the primitive pixels into retained pixels and discarded pixels. The retained pixels each corresponds to a mask pixel that the coverage data indicates is a covered pixel and the discarded pixels each correspond to a mask pixels that the coverage data indicates is an uncovered pixel. The system also includes an attribute generator configured to generate pixel attributes for the retained primitive pixels and also configured not to generate pixel attributes for the discarded primitive pixels.
摘要翻译：该系统包括形状缓冲器管理器，其被配置为将覆盖数据存储在形状缓冲器中。覆盖数据指示每个掩模像素是被覆盖像素还是未覆盖像素。当要在屏幕上呈现的形状覆盖掩模像素使得满足一个或多个覆盖准则并且当形状不覆盖掩模像素时是未被覆盖的像素，使得一个或多个覆盖标准满足。边界原始光栅化器被配置为光栅化限制形状的边界原语。边界原语被光栅化为原始像素，每个像素对应于一个掩码像素。像素筛选器被配置为使用来自形状缓冲器的覆盖数据来将原始像素屏蔽到保留的像素和丢弃的像素中。保留像素分别对应于覆盖数据指示为被覆盖像素的掩码像素，并且丢弃的像素各自对应于覆盖数据指示的掩模像素是未覆盖的像素。该系统还包括属性生成器，其被配置为生成被保留的原始像素的像素属性，并且还被配置为不为所丢弃的原始像素生成像素属性。

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