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1. 发明申请

US20100283497A1 SEMICONDUCTOR TESTING DEVICE, SEMICONDUCTOR DEVICE, AND TESTING METHOD 失效
标题翻译：半导体测试器件，半导体器件和测试方法
公开(公告)号：US20100283497A1
公开(公告)日：2010-11-11
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译：提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

2. 发明授权

US08441277B2 Semiconductor testing device, semiconductor device, and testing method 失效
标题翻译：半导体测试装置，半导体器件和测试方法
公开(公告)号：US08441277B2
公开(公告)日：2013-05-14
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译：提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

3. 发明申请

US20110260747A1 SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US20110260747A1
公开(公告)日：2011-10-27
申请号：US13139609
申请日：2009-12-22
申请人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
发明人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
IPC分类号： G01R31/26 , G05F1/10
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译：半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12）半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力，连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

4. 发明授权

US08513970B2 Semiconductor device and method of testing the same 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US08513970B2
公开(公告)日：2013-08-20
申请号：US13139609
申请日：2009-12-22
申请人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
发明人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译：半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12）半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力，连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

5. 发明授权

US08330254B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08330254B2
公开(公告)日：2012-12-11
申请号：US12647639
申请日：2009-12-28
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
IPC分类号： H01L23/544
CPC分类号： H01L23/48 , G01R31/2884 , G01R31/3025 , G01R31/31721 , H01L22/32 , H01L23/50 , H01L23/5286 , H01L23/544 , H01L24/06 , H01L2223/5446 , H01L2924/01029
摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.
摘要翻译：一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。

6. 发明申请

US20120025790A1 ELECTRONIC CIRCUIT, CIRCUIT APPARATUS, TEST SYSTEM, CONTROL METHOD OF THE ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路，电路设备，测试系统，电子电路控制方法
公开(公告)号：US20120025790A1
公开(公告)日：2012-02-02
申请号：US13146806
申请日：2010-02-09
申请人： Koichiro Noguchi , Koichi Nose , Yoshihiro Nakagawa , Masayuki Mizuno
发明人： Koichiro Noguchi , Koichi Nose , Yoshihiro Nakagawa , Masayuki Mizuno
IPC分类号： G05F1/10
CPC分类号： G01R31/31721 , G05F1/607
摘要： An electronic circuit includes: a first power line capable of supplying power; a second power line capable of supplying power independently from the first power line; a main circuit connected to the second power line; a detector that detects the supply of power from the first power line or the second power line; and a controller connected to the first power line and the second power line, wherein the controller controls a voltage or a current supplied from the first power line and supplies the voltage or the current to the main circuit when the detector detects supply of power from the first power line.
摘要翻译：电子电路包括：能够供电的第一电力线; 能够独立于所述第一电力线供电的第二电力线; 连接到第二电力线的主电路; 检测器，其检测来自所述第一电力线或所述第二电力线的电力供应; 以及连接到所述第一电力线和所述第二电力线的控制器，其中，所述控制器控制从所述第一电力线提供的电压或电流，并且当所述检测器检测到来自所述主电路的电力供应时，将电压或电流提供给所述主电路第一条电力线。

7. 发明申请

US20120062301A1 Control voltage generating circuit, constant current source circuit, and delay circuit and logic circuit including the same 有权
标题翻译：控制电压发生电路，恒流源电路以及延迟电路及逻辑电路均包括在内
公开(公告)号：US20120062301A1
公开(公告)日：2012-03-15
申请号：US13137744
申请日：2011-09-09
申请人： Koichiro Noguchi , Koichi Nose
发明人： Koichiro Noguchi , Koichi Nose
IPC分类号： H03K5/06
CPC分类号： H03K5/133 , H03K2005/00032 , H03K2005/00123
摘要： A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.
摘要翻译：根据本发明的一个方面的控制电压产生电路包括：参考电压单元，包括串联连接在第一电源和第二电源之间的多个相同导电类型的第一晶体管，并产生漏极电压作为参考电压的多个第一晶体管中的一个; 以及电压转换单元，其包括串联连接在第一电源和第二电源之间并具有与参考电压相同的导电类型的多个第二晶体管，将参考电压提供给多个并且将多个第二晶体管中的一个的漏极电压作为控制电压输出。

8. 发明授权

US08653861B2 Control voltage generating circuit, constant current source circuit, and delay circuit and logic circuit including the same 有权
标题翻译：控制电压发生电路，恒流源电路以及延迟电路及逻辑电路均包括在内
公开(公告)号：US08653861B2
公开(公告)日：2014-02-18
申请号：US13137744
申请日：2011-09-09
申请人： Koichiro Noguchi , Koichi Nose
发明人： Koichiro Noguchi , Koichi Nose
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K5/133 , H03K2005/00032 , H03K2005/00123
摘要： A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.
摘要翻译：根据本发明的一个方面的控制电压产生电路包括：参考电压单元，包括串联连接在第一电源和第二电源之间的多个相同导电类型的第一晶体管，并产生漏极电压作为参考电压的多个第一晶体管中的一个; 以及电压转换单元，其包括串联连接在第一电源和第二电源之间并且具有与参考电压相同的导电类型的多个第二晶体管，将参考电压提供给多个并且将多个第二晶体管中的一个的漏极电压作为控制电压输出。

9. 发明申请

US20120018726A1 SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体晶体管及半导体器件制造方法
公开(公告)号：US20120018726A1
公开(公告)日：2012-01-26
申请号：US13258884
申请日：2010-03-23
申请人： Yoshihiro Nakagawa , Koichi Nose , Koichiro Noguchi , Masamoto Tago , Shinichi Uchida , Yoshiyuki Sato
发明人： Yoshihiro Nakagawa , Koichi Nose , Koichiro Noguchi , Masamoto Tago , Shinichi Uchida , Yoshiyuki Sato
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L22/32 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor wafer in which a plurality of regions, designed to become semiconductor chips are provided in a matrix array with interposition of a dicing line(s) respectively separating the regions. The semiconductor wafer comprises: a plurality of test pads provided in an area(s) of the semiconductor wafer disposed between the semiconductor chips, inclusive of the dicing line(s); an inter-test pad interconnect(s) provided in parallel with the test pads in the area(s) of the semiconductor wafer disposed between the regions to become semiconductor chips; the inter-test pad interconnect(s) being connected to the test pads; and an inter-chip interconnect that interconnects at least two of the regions designed to become semiconductor chips; the inter-test pad interconnect being electrically connected to the inter-chip interconnect.
摘要翻译：设置成成为半导体芯片的多个区域的半导体晶片以分别分开该区域的切割线插入矩阵阵列中。半导体晶片包括：多个测试焊盘，设置在设置在半导体芯片之间的半导体晶片的区域中，包括切割线; 与设置在所述半导体芯片之间的半导体晶片的区域中的测试焊盘平行设置的测试间互连（inter-test pad interconnect）; 所述测试间互连连接到所述测试焊盘; 以及将设计成半导体芯片的区域中的至少两个互连的芯片间互连; 所述测试间互连件电连接到所述芯片间互连。

10. 发明授权

US08674774B2 Aging diagnostic device, aging diagnostic method 失效
标题翻译：老化诊断仪，老化诊断方法
公开(公告)号：US08674774B2
公开(公告)日：2014-03-18
申请号：US13394542
申请日：2010-09-01
申请人： Eisuke Saneyoshi , Koichi Nose , Masayuki Mizuno
发明人： Eisuke Saneyoshi , Koichi Nose , Masayuki Mizuno
IPC分类号： H03L7/24 , G01R31/28
CPC分类号： G01R31/2856 , G01R31/2882 , G01R31/2884 , H03K5/133
摘要： There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.
摘要翻译：提供了一种老化诊断装置，包括：构成使用CMOS电路构成的奇数多个逻辑门的环形振荡器的参考环形振荡器（101）使用具有与逻辑门相同配置的奇数多个逻辑门构成环形振荡器的测试环振荡器（102）; 负载单元（104），其向所述测试环形振荡器（102）输入负载信号; 控制单元（105），其同时将参考环形振荡器（101）和测试环形振荡器（102）的振荡开始的控制信号输入到参考环形振荡器（101）和测试环形振荡器（102）; 以及比较单元（103），其分别同时比较参考环形振荡器（101）和测试环形振荡器（102）中的脉冲的移动量的差异。

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