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1. 发明申请

US20120018726A1 SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体晶体管及半导体器件制造方法
公开(公告)号：US20120018726A1
公开(公告)日：2012-01-26
申请号：US13258884
申请日：2010-03-23
申请人： Yoshihiro Nakagawa , Koichi Nose , Koichiro Noguchi , Masamoto Tago , Shinichi Uchida , Yoshiyuki Sato
发明人： Yoshihiro Nakagawa , Koichi Nose , Koichiro Noguchi , Masamoto Tago , Shinichi Uchida , Yoshiyuki Sato
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L22/32 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor wafer in which a plurality of regions, designed to become semiconductor chips are provided in a matrix array with interposition of a dicing line(s) respectively separating the regions. The semiconductor wafer comprises: a plurality of test pads provided in an area(s) of the semiconductor wafer disposed between the semiconductor chips, inclusive of the dicing line(s); an inter-test pad interconnect(s) provided in parallel with the test pads in the area(s) of the semiconductor wafer disposed between the regions to become semiconductor chips; the inter-test pad interconnect(s) being connected to the test pads; and an inter-chip interconnect that interconnects at least two of the regions designed to become semiconductor chips; the inter-test pad interconnect being electrically connected to the inter-chip interconnect.
摘要翻译：设置成成为半导体芯片的多个区域的半导体晶片以分别分开该区域的切割线插入矩阵阵列中。半导体晶片包括：多个测试焊盘，设置在设置在半导体芯片之间的半导体晶片的区域中，包括切割线; 与设置在所述半导体芯片之间的半导体晶片的区域中的测试焊盘平行设置的测试间互连（inter-test pad interconnect）; 所述测试间互连连接到所述测试焊盘; 以及将设计成半导体芯片的区域中的至少两个互连的芯片间互连; 所述测试间互连件电连接到所述芯片间互连。

2. 发明授权

US08536890B2 Semiconductor inspecting device and semiconductor inspecting method 失效
标题翻译：半导体检测装置及半导体检查方法
公开(公告)号：US08536890B2
公开(公告)日：2013-09-17
申请号：US12865201
申请日：2009-02-05
申请人： Yoshio Kameda , Masamoto Tago , Yoshihiro Nakagawa , Koichiro Noguchi
发明人： Yoshio Kameda , Masamoto Tago , Yoshihiro Nakagawa , Koichiro Noguchi
IPC分类号： G01R31/20
CPC分类号： G01R31/303 , G01R31/2889 , G01R31/3025
摘要： A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.
摘要翻译：半导体检查装置包括用于向其中形成有一个或多个对象芯片的半导体晶片发送信号或电源的探针卡，并且构成为使得第一半导体晶片面向探针卡的第一面，并且使得第二半导体晶片面对第一面的相对侧的探针卡的第二面。探针卡包括一个或多个检查芯片，其可以执行与第一半导体晶片中的第一对象芯片和第二半导体晶片中的第二对象芯片的非接触传输。

3. 发明授权

US08570056B2 Semiconductor inspection apparatus, semiconductor wafer positioning method, and semiconductor wafer inspection method 失效
标题翻译：半导体检查装置，半导体晶片定位方法以及半导体晶片检查方法
公开(公告)号：US08570056B2
公开(公告)日：2013-10-29
申请号：US12866223
申请日：2009-02-26
申请人： Yoshio Kameda , Masamoto Tago , Yoshihiro Nakagawa , Koichiro Noguchi
发明人： Yoshio Kameda , Masamoto Tago , Yoshihiro Nakagawa , Koichiro Noguchi
IPC分类号： G01R31/00 , G01R31/02
CPC分类号： G01R31/2891
摘要： A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirectly secure the corresponding semiconductor wafers and that possess a mechanism for positioning the corresponding semiconductor wafers; and a probe card, arranged outside or in between the plurality of laminated semiconductor wafers so as to face the semiconductor wafers, that transmits a signal or power to the plurality of semiconductor wafers.
摘要翻译：一种半导体检查装置，包括：对于多个层叠半导体晶片中的每一个独立设置的多个晶片台，其直接或间接固定相应的半导体晶片，并且具有用于定位相应的半导体晶片的机构; 以及探针卡，其布置在多个层叠半导体晶片之间或之间，以面对半导体晶片，其向多个半导体晶片发送信号或电力。

4. 发明申请

US20100321054A1 SEMICONDUCTOR INSPECTING DEVICE AND SEMICONDUCTOR INSPECTING METHOD 失效
标题翻译：半导体检测器件和半导体检测方法
公开(公告)号：US20100321054A1
公开(公告)日：2010-12-23
申请号：US12865201
申请日：2009-02-05
申请人： Yoshio Kameda , Masamoto Tago , Yoshihiro Nakagawa , Koichiro Noguchi
发明人： Yoshio Kameda , Masamoto Tago , Yoshihiro Nakagawa , Koichiro Noguchi
IPC分类号： G01R31/20 , G01R31/26
CPC分类号： G01R31/303 , G01R31/2889 , G01R31/3025
摘要： A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.
摘要翻译：半导体检查装置包括用于向其中形成有一个或多个对象芯片的半导体晶片发送信号或电源的探针卡，并且构成为使得第一半导体晶片面向探针卡的第一面，并且使得第二半导体晶片面对第一面的相对侧的探针卡的第二面。探针卡包括一个或多个检查芯片，其可以执行与第一半导体晶片中的第一对象芯片和第二半导体晶片中的第二对象芯片的非接触传输。

5. 发明申请

US20120025790A1 ELECTRONIC CIRCUIT, CIRCUIT APPARATUS, TEST SYSTEM, CONTROL METHOD OF THE ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路，电路设备，测试系统，电子电路控制方法
公开(公告)号：US20120025790A1
公开(公告)日：2012-02-02
申请号：US13146806
申请日：2010-02-09
申请人： Koichiro Noguchi , Koichi Nose , Yoshihiro Nakagawa , Masayuki Mizuno
发明人： Koichiro Noguchi , Koichi Nose , Yoshihiro Nakagawa , Masayuki Mizuno
IPC分类号： G05F1/10
CPC分类号： G01R31/31721 , G05F1/607
摘要： An electronic circuit includes: a first power line capable of supplying power; a second power line capable of supplying power independently from the first power line; a main circuit connected to the second power line; a detector that detects the supply of power from the first power line or the second power line; and a controller connected to the first power line and the second power line, wherein the controller controls a voltage or a current supplied from the first power line and supplies the voltage or the current to the main circuit when the detector detects supply of power from the first power line.
摘要翻译：电子电路包括：能够供电的第一电力线; 能够独立于所述第一电力线供电的第二电力线; 连接到第二电力线的主电路; 检测器，其检测来自所述第一电力线或所述第二电力线的电力供应; 以及连接到所述第一电力线和所述第二电力线的控制器，其中，所述控制器控制从所述第一电力线提供的电压或电流，并且当所述检测器检测到来自所述主电路的电力供应时，将电压或电流提供给所述主电路第一条电力线。

6. 发明申请

US20110260747A1 SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US20110260747A1
公开(公告)日：2011-10-27
申请号：US13139609
申请日：2009-12-22
申请人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
发明人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
IPC分类号： G01R31/26 , G05F1/10
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译：半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12）半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力，连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

7. 发明授权

US08513970B2 Semiconductor device and method of testing the same 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US08513970B2
公开(公告)日：2013-08-20
申请号：US13139609
申请日：2009-12-22
申请人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
发明人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译：半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12）半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力，连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

8. 发明申请

US20100194423A1 APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE TO BE TESTED 审中-公开
标题翻译：用于测试要测试的半导体和半导体器件的装置和方法
公开(公告)号：US20100194423A1
公开(公告)日：2010-08-05
申请号：US12679959
申请日：2008-09-26
申请人： Masamoto Tago , Yoshihiro Nakagawa
发明人： Masamoto Tago , Yoshihiro Nakagawa
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R31/3025 , H01L21/6836 , H01L22/32 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05624 , H01L2224/16 , H01L2924/00014 , H01L2924/1461 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Provided is a semiconductor testing apparatus which can perform batch test of semiconductor wafers. In the semiconductor testing apparatus, an LSI apparatus for conducting a test and which provided with a circuit and an electrode for transmitting noncontact signals, and a probe card to which a contact-type probe pin is attached are separately arranged. The semiconductor testing apparatus is provided with a recognition unit for precisely aligning the electrodes of the LSI apparatus for conducting a test, the LSI wafer to be tested and the probe card. The LSI apparatus for conducting a test and a probe pin of the probe card are mounted on a stage or a pressurizing head, and contact can be made to sandwich an LSI wafer to be tested, from both the front surface and the rear surface of the LSI wafer to be tested at the same time.
摘要翻译：提供了可以进行半导体晶片的批量测试的半导体测试装置。在半导体测试装置中，分别设置用于进行测试并且设置有用于发送非接触信号的电路和电极以及安装有接触型探针的探针卡的LSI装置。半导体测试装置设置有用于精确对准用于进行测试的LSI装置的电极，待测试的LSI晶片和探针卡的识别单元。用于进行测试的LSI装置和探针卡的探针安装在平台或加压头上，并且可以将接触从夹具中的待测试的LSI晶片两者的两个表面和背面 LSI晶圆同时进行测试。

9. 发明授权

US08330254B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08330254B2
公开(公告)日：2012-12-11
申请号：US12647639
申请日：2009-12-28
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
IPC分类号： H01L23/544
CPC分类号： H01L23/48 , G01R31/2884 , G01R31/3025 , G01R31/31721 , H01L22/32 , H01L23/50 , H01L23/5286 , H01L23/544 , H01L24/06 , H01L2223/5446 , H01L2924/01029
摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.
摘要翻译：一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。

10. 发明授权

US08399960B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08399960B2
公开(公告)日：2013-03-19
申请号：US12920381
申请日：2009-02-20
申请人： Yoshihiro Nakagawa , Koichiro Noguchi , Yoshio Kameda , Masayuki Mizuno
发明人： Yoshihiro Nakagawa , Koichiro Noguchi , Yoshio Kameda , Masayuki Mizuno
IPC分类号： H01L27/08
CPC分类号： H01L27/0688 , H01L23/48 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2225/06527 , H01L2924/00014 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A plurality of semiconductor chips are juxtaposed, each having an electromagnetic induction coil disposed thereon. A signal is transmitted by way of electromagnetic induction between the electromagnetic induction coils disposed on a pair of adjacent semiconductor chips.
摘要翻译：多个半导体芯片并置，每个具有布置在其上的电磁感应线圈。在布置在一对相邻半导体芯片上的电磁感应线圈之间通过电磁感应传输信号。

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