专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5539739A Asynchronous interface between parallel processor nodes 失效
标题翻译：并行处理器节点之间的异步接口
公开(公告)号：US5539739A
公开(公告)日：1996-07-23
申请号：US315284
申请日：1994-09-29
申请人： Charles Dike , Robert Gatlin , Jerry Jex , Craig Peterson , Keith Self , Jim Sutton
发明人： Charles Dike , Robert Gatlin , Jerry Jex , Craig Peterson , Keith Self , Jim Sutton
IPC分类号： G06F15/173 , H04L7/04
CPC分类号： G06F15/17381
摘要： An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.
摘要翻译：异步接口使处理器节点能够以第一时钟频率工作，以便以第二时钟频率工作的通信网络传送和接收信息。异步接口包括输入同步器和输出同步器。输入同步器异步地从处理器节点接收第一多个信息分组，并且将第一多个信息分组同步地传送到通信网络中。然而，输出同步器同步地从通信网络接收第二多个信息分组，并将第二多个信息分组异步传送到处理器节点。输入和输出同步器都连接在通信网络和处理器节点之间。

2. 发明授权

US5598113A Fully asynchronous interface with programmable metastability settling time synchronizer 失效
标题翻译：具有可编程亚稳态建立时间同步器的完全异步接口
公开(公告)号：US5598113A
公开(公告)日：1997-01-28
申请号：US375361
申请日：1995-01-19
申请人： Jerry Jex , Charles Dike , Keith Self
发明人： Jerry Jex , Charles Dike , Keith Self
IPC分类号： G06F5/06 , H04J3/04 , H03K19/00 , H03K5/135
CPC分类号： G06F5/06 , H04J3/047
摘要： A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.
摘要翻译：具有分级写入和读取功能的完全异步并行同步器使能和异步接口相同。异步接口可用于互连两个处理器系统（例如，在多处理器系统或并行处理器系统内）。并行可编程同步器包含并联耦合的n个锁存器，其具有具有交错使能信号的n个单独使能线。锁存器被耦合，使得它们输出到多路复用电路，该多路复用电路还接收基于写入使能信号的单独的交错读取使能信号。根据并行可编程同步器，在紧随其后的时钟周期（i-1）中从相同的特定锁存器读取其它数据之后，数据被写入时钟周期（i）中的特定锁存器。虽然同步器包含n个锁存器，但是对于任何特定实施例，所使用的锁存器的数量x是可编程的，并且使能信号被调整以适应所选择的锁存器的数量。因此，同步器的建立时间是可编程的，而同步器也提供最大吞吐量频率（采样率）。还描述了一个新的空旗生成。

3. 发明申请

US20050018761A1 Transmitters providing cycle encoded signals 有权
标题翻译：发射机提供循环编码信号
公开(公告)号：US20050018761A1
公开(公告)日：2005-01-27
申请号：US10625945
申请日：2003-07-23
申请人： Jerry Jex , Jed Griffin , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jerry Jex , Jed Griffin , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H04L27/24 , H04B1/38
CPC分类号： H04L25/4904 , H04L25/0272 , H04L27/24
摘要： In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal. Still other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括发射机，其包括用于接收数据输入信号的周期编码电路，并通过连续地连接不同编码信号的部分来响应于此提供全周期编码信号。编码信号中的一些具有与编码信号的其他编码信号不同的频率，并且一些编码信号与编码信号的其它信号具有不同的相位。数据在全周期编码信号的数据时间段中表示，并且没有数据时间段具有多于一个编码信号的周期。在一些实施例中，接收器接收周期编码信号并恢复数据输入信号的数据。还描述和要求保护其他实施例。

4. 发明申请

US20050018779A1 Receivers for cycle encoded signals 有权
标题翻译：接收器用于循环编码信号
公开(公告)号：US20050018779A1
公开(公告)日：2005-01-27
申请号：US10625944
申请日：2003-07-23
申请人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H04L1/06 , H04L25/49 , H04L27/24 , H04L27/00
CPC分类号： H04L27/24 , H04L1/06 , H04L25/4904
摘要： In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括接收器，用于接收全周期编码信号，其中在数据时间段中表示数据，并且没有数据时间段具有多于一个周期。接收机响应于全周期编码信号提供数据输出信号。描述和要求保护其他实施例。

5. 发明申请

US20080101505A1 RECEIVERS FOR CYCLE ENCODED SIGNALS 有权
标题翻译：循环编码信号的接收器
公开(公告)号：US20080101505A1
公开(公告)日：2008-05-01
申请号：US11925474
申请日：2007-10-26
申请人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H04L7/00 , H04L27/06
CPC分类号： H04L27/24 , H04L1/06 , H04L25/4904
摘要： In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.
摘要翻译：在一些实施例中，本发明包括发射机，其包括用于接收数据输入信号的周期编码电路，并通过连续地连接不同编码信号的部分来响应于此提供全周期编码信号。编码信号中的一些具有与编码信号的其他编码信号不同的频率，并且一些编码信号与编码信号的其它信号具有不同的相位。数据在全周期编码信号的数据时间段中表示，并且没有数据时间段具有多于一个编码信号的周期。在一些实施例中，接收器接收周期编码信号并恢复数据输入信号的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式