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1. 发明申请

US20100253406A1 APPARATUS AND METHOD FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION OF THE TIME DELAY OF A DIGITAL DELAY LINE 有权
标题翻译：用于补偿数字延迟线时间延迟的过程，电压和温度变化的装置和方法
公开(公告)号：US20100253406A1
公开(公告)日：2010-10-07
申请号：US12418981
申请日：2009-04-06
申请人： James Seefeldt , Xiaoxin Feng , Weston Roper
发明人： James Seefeldt , Xiaoxin Feng , Weston Roper
IPC分类号： H03L1/00 , H03L7/00 , G01R25/00
CPC分类号： G11C29/022 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4072 , G11C11/4093 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
摘要翻译：提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。补偿电路包括两个延迟线，每个延迟线提供延迟输出。两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。延迟线的数量可能在两个延迟线之间不同。延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM，处理器或其他时钟电路。

2. 发明授权

US08390352B2 Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line 有权
标题翻译：用于补偿数字延迟线的时间延迟的过程，电压和温度变化的装置和方法
公开(公告)号：US08390352B2
公开(公告)日：2013-03-05
申请号：US12418981
申请日：2009-04-06
申请人： James Seefeldt , Xiaoxin Feng , Weston Roper
发明人： James Seefeldt , Xiaoxin Feng , Weston Roper
IPC分类号： H03L7/00
CPC分类号： G11C29/022 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4072 , G11C11/4093 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
摘要翻译：提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。补偿电路包括两个延迟线，每个延迟线提供延迟输出。两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。延迟线的数量可能在两个延迟线之间不同。延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM，处理器或其他时钟电路。

3. 发明申请

US20070090891A1 Power supply compensated voltage and current supply 有权
标题翻译：电源补偿电压和电流供应
公开(公告)号：US20070090891A1
公开(公告)日：2007-04-26
申请号：US11254473
申请日：2005-10-20
申请人： James Seefeldt
发明人： James Seefeldt
IPC分类号： H03L7/099
CPC分类号： H03K5/133 , H03K2005/0013 , H03L7/0995
摘要： An apparatus and method for providing a power supply compensted voltage or current is presented. A supply compensated current and voltage source utilizes a differential amplifier connected to a bandgap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator.
摘要翻译：提出了一种用于提供补偿电压或电流的电源的装置和方法。电源补偿电流和电压源使用连接到带隙参考电压和缩放电源电压的差分放大器。当电源变化时，差分放大器调节稳定的补偿输出。输出可以是补偿电压或电流。此外，可以从差分放大器参考多个电流和电压。稳定的补偿输出可以作为外部电路的参考偏置来提供。此外，补偿输出可以被提供给压控振荡器。

4. 发明授权

US06220101B1 Apparatus for measuring multiple pressures 失效
标题翻译：用于测量多重压力的装置
公开(公告)号：US06220101B1
公开(公告)日：2001-04-24
申请号：US09241959
申请日：1999-02-02
申请人： James Schloss , James Seefeldt , Carol Spicuzza , Gary Ryall , Wendell McCulley , Paul Rozgo , Jesse Marcelle
发明人： James Schloss , James Seefeldt , Carol Spicuzza , Gary Ryall , Wendell McCulley , Paul Rozgo , Jesse Marcelle
IPC分类号： G01L700
CPC分类号： G01L15/00
摘要： The apparatus includes a housing; a plurality of sensors mounted on the housing, each of the sensors including a sensing element and an electrical output connected to said sensing element. The apparatus also includes a plurality of inputs connected to the sensors, respectively, to transmit to the sensors. A circuit is mounted in the housing and in electrical connection with the electrical outputs to provide a common signal conditioner for the sensors.
摘要翻译：该装置包括壳体; 安装在壳体上的多个传感器，每个传感器包括感测元件和连接到所述感测元件的电输出。该装置还包括分别连接到传感器以传输到传感器的多个输入。电路安装在壳体中并与电输出端电连接，为传感器提供公共信号调节器。

5. 发明申请

US20070090887A1 Lock detect circuit for a phase locked loop 有权
标题翻译：用于锁相环路的锁定检测电路
公开(公告)号：US20070090887A1
公开(公告)日：2007-04-26
申请号：US11254569
申请日：2005-10-20
申请人： James Seefeldt , Bradley Kantor
发明人： James Seefeldt , Bradley Kantor
IPC分类号： H03L7/00
CPC分类号： H03D13/004 , H03L7/095 , Y10S331/02
摘要： An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.
摘要翻译：描述了用于确定锁相环（PLL）的锁定状态的改进的系统和方法。锁定检测电路产生快速锁定检测信号，其可用于检测瞬时的锁定损失。锁定检测电路还可以包括相位对准检测电路，用于检测参考时钟和反馈时钟的相位中的未对准。此外，锁定检测电路可以包括参考时钟检测电路，以检测是否检测到参考时钟信号。来自所有上述电路的输出信号可以被传送到逻辑电路，以便产生增强的锁定检测信号。扩展锁定检测信号也可以被传送到逻辑电路。

6. 发明申请

US20070090881A1 Circuit to reset a phase locked loop after a loss of lock 有权
标题翻译：电路在锁定失败后复位锁相环
公开(公告)号：US20070090881A1
公开(公告)日：2007-04-26
申请号：US11254474
申请日：2005-10-20
申请人： James Seefeldt
发明人： James Seefeldt
IPC分类号： H03L7/085
CPC分类号： H03L7/105 , H03L7/095 , H03L7/10 , Y10S331/02
摘要： A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into reset circuitry. The reset circuitry within the PLL comprises a series of interconnected latches, or D flip-flops, which are used to create a delay time. The delay time is the amount of time the reset circuit will wait until the reset signal indicates a reset. The reset circuit may also generate a reset signal having a pulse width. The pulse width is determined by the series of interconnected latches. The reset signal may be used to reset a Voltage Controlled Oscillator (VCO) or other circuits within a PLL or it may be used by circuits external to the PLL.
摘要翻译：描述了在锁相环（PLL）电路内产生复位信号的系统和方法。通过将参考信号和锁定检测信号输入复位电路来产生复位信号。 PLL内的复位电路包括一系列互连的锁存器或D触发器，用于产生延迟时间。延迟时间是复位电路等待复位信号指示复位的时间量。复位电路还可以产生具有脉冲宽度的复位信号。脉冲宽度由一系列互连的锁存器确定。复位信号可用于复位压控振荡器（VCO）或PLL内的其他电路，或者可由PLL外部的电路使用复位信号。

7. 发明申请

US20070176655A1 Differential charge pump with open loop common mode 有权
标题翻译：差动电荷泵与开环共模
公开(公告)号：US20070176655A1
公开(公告)日：2007-08-02
申请号：US11342106
申请日：2006-01-27
申请人： Mark Dvorak , James Hiller , James Seefeldt
发明人： Mark Dvorak , James Hiller , James Seefeldt
IPC分类号： H03L7/06
CPC分类号： H03L7/0896
摘要： A differential charge pump with common mode and active regulators is presented. Either type of regulator may be used to improve the performance characteristics of the differential charge pump. The active regulator increases the output range of the differential amplifier. The common mode regulator establishes the common mode voltage of the differential charge pump. The common mode voltage is established independently from external circuitry and does not use a feedback path. The common mode regulator may also be used to establish a mid-rail voltage, which may be used to further improve the output range of the differential amplifier.
摘要翻译：提出了一种具有共模和主动调节器的差动电荷泵。可以使用任一类型的调节器来改善差动电荷泵的性能特征。有源稳压器增加了差分放大器的输出范围。共模调节器建立差动电荷泵的共模电压。共模电压独立于外部电路建立，不使用反馈路径。共模调节器也可以用于建立中间轨电压，其可以用于进一步改善差分放大器的输出范围。

8. 发明申请

US20070090890A1 Voltage-controlled oscillator with stable gain over a wide frequency range 有权
标题翻译：在宽频率范围内稳压增益的压控振荡器
公开(公告)号：US20070090890A1
公开(公告)日：2007-04-26
申请号：US11254466
申请日：2005-10-20
申请人： James Seefeldt
发明人： James Seefeldt
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03B5/02 , H03L7/0995 , H03L7/10 , H03L7/18
摘要： An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.
摘要翻译：提出了一种在VCO中在宽频率范围内提供稳定增益的装置和方法。 VCO使用波形发生器以及具有频率选择输入的偏置发生器。频率选择输入用于调整偏置发生器的输出电流和/或增益的量。偏置发生器的输出电流决定了波形发生器的输出频率。可以使用多个偏置和波形发生器来扩展VCO的频率范围。通过使用VCO的频率选择输入，PLL可以针对各种输出频率进行编程。

9. 发明申请

US20050212071A1 Techniques to reduce substrate cross talk on mixed signal and RF circuit design 有权
标题翻译：降低混合信号和RF电路设计的基板串扰技术
公开(公告)号：US20050212071A1
公开(公告)日：2005-09-29
申请号：US10811207
申请日：2004-03-26
申请人： Cheisan Yue , James Seefeldt
发明人： Cheisan Yue , James Seefeldt
IPC分类号： H01L21/762 , H01L21/765 , H01L29/732
CPC分类号： H01L21/76283 , H01L21/765 , H01L21/84 , H01L27/1203
摘要： An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.
摘要翻译：集成电路具有形成在半导体衬底上的掩埋绝缘层和形成在掩埋绝缘层上的半导体台面。低电阻率保护环基本上围绕半导体台面并与半导体衬底接触。低电阻率保护环接地，并将半导体台面与RF信号隔离开来。

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