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1. 发明授权

US5780904A Semiconductor integrated circuit device for obtaining extremely small constant current and timer circuit using constant current circuit 失效
标题翻译：用于获得极小的恒流和使用恒流电路的定时器电路的半导体集成电路器件
公开(公告)号：US5780904A
公开(公告)日：1998-07-14
申请号：US671941
申请日：1996-06-28
申请人： Haruo Konishi , Masanao Hamaguchi , Masanori Miyagi
发明人： Haruo Konishi , Masanao Hamaguchi , Masanori Miyagi
IPC分类号： G05F3/24 , G05F3/26 , G11C11/406 , H03F3/343 , H03F3/347 , H01L27/06
CPC分类号： G05F3/262
摘要： To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first constant current, a second constant-current source connected to the first constant-current source for producing a second constant current having a different value from that of the first current, and an output terminal from which a third constant current equal to the difference between the first and second constant currents is output, such that the third constant current having an extremely small value may be produced without the use of a constant current source capable of producing an extremely small constant current value. The first and second constant current sources may be connected in series with the output terminal connected therebetween, or in parallel through a current mirror circuit. In addition, the constant current circuit can be provided in a timer circuit to produce a very long constant time signal with great stability. In one embodiment, such a timer circuit further includes a capacitor connected to the output terminal for receiving the third constant current and accumulating charge, a reference voltage generator for producing a reference voltage, and a voltage comparator for comparing the voltage of the capacitor with the reference voltage.
摘要翻译：为了以高精度获得极小的恒定电流，恒流电路包括用于产生第一恒定电流的第一恒流源，连接到第一恒流源的第二恒流源，用于产生具有第二恒定电流的第二恒定电流，与第一电流不同的值以及输出等于第一和第二恒定电流之间的差的第三恒定电流的输出端子，使得可以产生具有极小值的第三恒定电流，而不需要使用能够产生非常小的恒定电流值的恒定电流源。第一和第二恒流源可以与连接在它们之间的输出端子串联连接，或者通过电流镜电路并联连接。此外，恒定电流电路可以提供在定时器电路中以产生非常长的恒定时间信号，具有很大的稳定性。在一个实施例中，这种定时器电路还包括连接到输出端子的电容器，用于接收第三恒定电流并累积电荷，用于产生参考电压的参考电压发生器和用于将电容器的电压与参考电压。

2. 发明授权

US06498376B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06498376B1
公开(公告)日：2002-12-24
申请号：US08459831
申请日：1995-06-02
申请人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
发明人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
IPC分类号： H01L2976
CPC分类号： H01L29/78696 , H01L21/3226 , H01L21/823462 , H01L27/0705 , H01L29/1041 , H01L29/1045 , H01L29/66757
摘要： A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.
摘要翻译： MISFET设置有分段通道，该分段通道包括其中通道被第一栅极电压反相的区域和通道以第二栅极电压反相的区域。 MISFET形成在具有第一导电类型的半导体衬底中，沟道的第一反相区域具有由衬底的表面浓度确定的第一杂质浓度。通道的第二反转区域具有通过将杂质掺杂到通过光刻工艺选择的区域而确定的第二杂质浓度。第一反转区域和第二反转区域可以被划分成多个平面形状，并且根据第一和第二反转区域的平面面积比将MISFET的阈值电压设置为期望值。

3. 发明授权

US06306709B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06306709B1
公开(公告)日：2001-10-23
申请号：US09270648
申请日：1999-03-16
申请人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
发明人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L21/3226 , H01L21/823462 , H01L27/0705 , H01L29/1041 , H01L29/1045 , H01L29/66757
摘要： In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.
摘要翻译：在MISFET中，在MISFET的沟道区域中设置沟道区域的沟道表面被第一栅极电压反转的区域和沟道表面由第二栅极电压反转的区域，作为其组成。具有由P型半导体衬底的表面浓度确定的第一杂质浓度的通道区域104和通过掺杂杂质确定的第二杂质浓度的沟道区域105，所述沟道区域105由用于掺杂杂质的掩模的图案106选择的区域通过离子注入等设置在P型半导体衬底上的N型MOSFET的沟道区中。具有第一杂质浓度的沟道区域104和具有第二杂质浓度的沟道区域105被分成多个平面形状。相同MOSFET的沟道区域可以由具有如上所述的多个杂质浓度的多个平面形状构成，并且可以根据区域的平面面积比容易地将MOSFET的阈值电压设置为期望值具有第一杂质浓度和具有第二杂质浓度的面积，从而以低成本实现高性能半导体集成电路器件。

4. 发明授权

US5905291A MISFET semiconductor integrated circuit device 失效
标题翻译： MISFET半导体集成电路器件
公开(公告)号：US5905291A
公开(公告)日：1999-05-18
申请号：US503828
申请日：1995-07-18
申请人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
发明人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
IPC分类号： H01L21/8247 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H01L29/772
CPC分类号： H01L27/0214 , H01L27/0629
摘要： A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
摘要翻译：半导体集成电路器件包括形成在半导体衬底上并以二极管连接串联连接的至少两个MISFET。每个MISFET具有源极，漏极，在源极和漏极之间延伸的沟道，以及通过栅极绝缘膜设置在沟道上方的栅极。一个MISFET具有第一阈值电压，另一个MISFET具有低于第一阈值电压的第二阈值电压。每个MISFET的半导体衬底的沟道的一部分具有等于或小于6×10 14原子/ cc的杂质浓度。

5. 发明申请

US20140186549A1 POWDER SUPPLY NOZZLE AND OVERLAYING METHOD 审中-公开
标题翻译：粉末供应喷嘴和覆盖方法
公开(公告)号：US20140186549A1
公开(公告)日：2014-07-03
申请号：US14239979
申请日：2012-08-09
申请人： Masanori Miyagi , Takeshi Tsukamoto , Hirotugu Kawanaka , Kenichi Okamoto
发明人： Masanori Miyagi , Takeshi Tsukamoto , Hirotugu Kawanaka , Kenichi Okamoto
IPC分类号： C23C4/12 , B05B1/24
CPC分类号： B05B1/24 , B23K26/144 , B23K26/342 , C23C4/123
摘要： An object of the present invention is to provide a powder supply nozzle and an overlaying method which make it possible to restrain oxidation of a clad layer part and to produce a clad layer part with high quality. The invention provides a powder supply nozzle including: a laser emission part for irradiating a workpiece with a laser beam; and a powder supply part disposed in the periphery of the laser emission part and adapted to discharge a powder onto a laser-irradiated part, wherein a mechanism for guiding the air surrounding the laser-irradiated part to the exterior of the laser-irradiated part is provided in the periphery of the powder supply part.
摘要翻译：本发明的目的是提供一种粉末供给喷嘴和覆盖方法，其可以抑制包覆层部分的氧化并产生高质量的包层部分。本发明提供了一种粉末供给喷嘴，包括：用激光束照射工件的激光发射部分; 以及粉末供给部，其设置在所述激光发射部的周围，并且适于将粉末喷射到激光照射部上，其中，将激光照射部分周围的空气引导到所述激光照射部的外部的机构是设置在粉末供给部的周边。

6. 发明申请

US20060066348A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20060066348A1
公开(公告)日：2006-03-30
申请号：US11226585
申请日：2005-09-14
申请人： Masanori Miyagi
发明人： Masanori Miyagi
IPC分类号： H03K19/0175
CPC分类号： H03K17/08122 , H03K17/063 , H03K19/018507
摘要： In an integrated circuit having two circuits operating at different power supply voltages a level shifter, which transmits a signal from a high voltage operation circuit to a low voltage operation circuit, is composed of a depletion NMOS transistor with its gate electrode fixed to the potential of the power supply voltage of the low voltage operation circuit.
摘要翻译：在具有以不同电源电压工作的两个电路的集成电路中，将从高电压操作电路传输信号的电平移位器组成为耗尽型NMOS晶体管，其栅电极固定为低压运行电路的电源电压。

7. 发明授权

US06566928B1 Latch circuit 有权
公开(公告)号：US06566928B1
公开(公告)日：2003-05-20
申请号：US09638197
申请日：2000-08-11
申请人： Masanori Miyagi
发明人： Masanori Miyagi
IPC分类号： H03K3037
CPC分类号： H03K17/223 , H03K3/0375
摘要： A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply. In addition the stopped system is not unnecessarily reset until the power supply is interrupted. As a consequence, it is possible to obtain the safety operation as well as the firm operation of the circuit and the system.

8. 发明授权

US06330204B1 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US06330204B1
公开(公告)日：2001-12-11
申请号：US09497013
申请日：2000-02-02
申请人： Masanori Miyagi
发明人： Masanori Miyagi
IPC分类号： G11C700
CPC分类号： G11C16/22 , G11C17/18
摘要： A memory circuit is provided which is capable of writing data with a simplified configuration and hence being improved in usability. The present invention comprises a fuse 10 having one end to which a bias voltage Vcc is to be applied from an internal power supply to have a disconnect/connect state storing data 0/1, a thyristor 11 having an anode terminal connected to the internal power supply through the fuse 10 and a cathode terminal being ground, an N-channel MOS transistor 12 having a drain terminal connected to a gate terminal of the thyristor 11 and a source terminal being ground, and a read-out circuit 14 for reading out data 0/1 stored on the fuse 10 through the N-channel MOS transistor 13.
摘要翻译：提供一种存储电路，其能够以简化的配置写入数据，因此在可用性方面得到改进。本发明包括一个保险丝10，其一端具有从内部电源施加偏置电压Vcc以具有断开/连接状态存储数据0/1，具有通过熔丝10连接到内部电源的阳极端子和正在接地的阴极端子的晶闸管11，具有连接到栅极端子的漏极端子的N沟道MOS晶体管12 和一个源极端子接地的读出电路14，用于通过N沟道MOS晶体管13读出存储在熔丝10上的数据0/1的读出电路14。

9. 发明授权

US06859040B2 Voltage detecting circuit 有权
标题翻译：电压检测电路
公开(公告)号：US06859040B2
公开(公告)日：2005-02-22
申请号：US10245517
申请日：2002-09-17
申请人： Masanori Miyagi
发明人： Masanori Miyagi
IPC分类号： G05F1/10 , G01R19/165 , G05F3/26 , H03K17/30 , G01R31/08
CPC分类号： G01R19/16519 , G01R19/16552
摘要： There is provided a voltage detecting circuit in which a consumed electric current is small, accuracy is high, and an erroneous operation seldom occurs. In the voltage detecting circuit constituted by a bias circuit, a current mirror circuit, a load MIS transistor connected to the current mirror circuit in which current drive capability is changed by an output voltage of the bias circuit, and an amplifying inverter circuit, a potential change at an output node of the current mirror circuit at the time of detection and release of a power supply voltage is steeply changed, so that a leak current of the whole circuit can be decreased and a consumed electric current can be reduced. Besides, plural load P type MIS transistors of the bias circuit are prepared, so that a detection voltage and a release voltage can be made to have hysteresis, abnormal oscillation of a detection output VDETX in the vicinity of the detection and release voltage can be prevented, and an erroneous operation of a logic circuit to which the detection output is applied can be prevented.
摘要翻译：提供了一种电压检测电路，其中消耗电流小，精度高，并且很少发生错误操作。在由偏置电路，电流镜电路，连接到电流镜电路的负载MIS晶体管中构成的电压检测电路中，电流驱动能力通过偏置电路的输出电压而变化，以及放大反相器电路，电位在检测到电流镜电路的输出节点处的变化急剧地改变电源电压的释放，从而可以减小整个电路的漏电流并消耗电流。此外，准备偏置电路的多个负载P型MIS晶体管，使得可以使检测电压和释放电压具有迟滞，可以防止检测和释放电压附近的检测输出VDETX的异常振荡并且可以防止应用检测输出的逻辑电路的错误操作。

10. 发明授权

US6163191A Writing signal timer output circuit which includes a bistable timer signal generator 失效
标题翻译：写入信号定时器输出电路，包括双稳态定时器信号发生器
公开(公告)号：US6163191A
公开(公告)日：2000-12-19
申请号：US94969
申请日：1998-06-12
申请人： Masanori Miyagi
发明人： Masanori Miyagi
IPC分类号： G11C16/02 , G11C16/06 , H03K3/0231 , H03K17/284 , H03K3/356
CPC分类号： H03K17/284 , H03K3/0231
摘要： In a non-volatile memory capable of electrically rewriting data, a timer circuit for determining writing time that is operable at any time at a voltage of under 1.0 V. The timing circuit has a regulated voltage circuit for outputting a regulated output voltage no greater than 1.0 V, a constant current circuit for producing a constant current having a value determined by the regulated output voltage, a voltage comparing circuit for comparing an input voltage input to one terminal with a reference voltage input to another terminal, and a capacitive element connected to a constant current output terminal of the constant current circuit. A connecting point of the constant current output terminal of the constant current circuit and the capacitive element is connected as the input voltage to the voltage comparing circuit, so that a desired time period is determined by comparing a voltage to the terminal of the voltage comparing circuit connected to the capacitive element with the reference voltage connected to the other terminal of the comparing circuit.
摘要翻译：在能够电气重写数据的非易失性存储器中，定时器电路用于确定在1.0V的电压下随时可操作的写入时间。定时电路具有调节电压电路，用于输出不大于 1.0V，用于产生具有由调节输出电压确定的值的恒定电流的恒流电路，用于将输入到一个端子的输入电压与输入到另一个端子的参考电压进行比较的电压比较电路和连接到恒流电路的恒流输出端。将恒流电路和电容元件的恒流输出端子的连接点作为输入电压连接到电压比较电路，从而通过将电压与电压比较电路的端子进行比较来确定期望的时间段连接到电容元件，参考电压连接到比较电路的另一端。

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