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1. 发明授权

US06532169B1 SONOS latch and application 有权
标题翻译： SONOS锁存和应用
公开(公告)号：US06532169B1
公开(公告)日：2003-03-11
申请号：US09892164
申请日：2001-06-26
申请人： Eric N. Mann , John Kizziar
发明人： Eric N. Mann , John Kizziar
IPC分类号： G11C1600
CPC分类号： G11C14/00 , G11C16/24 , G11C16/28
摘要： An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.
摘要翻译：一种包括锁存电路，非易失性存储电路和开关电路的装置。锁存电路可以被配置为可动态编程。非易失性存储电路可以被配置为可重新编程。开关电路可以被配置为响应于第一控制信号将数据从（i）非易失性存储器元件传送到锁存电路，以及（ii）响应于第二控制的锁存电路进入非易失性存储器电路信号。

2. 发明授权

US6088422A One-pin shift register interface 有权
标题翻译：单针移位寄存器接口
公开(公告)号：US6088422A
公开(公告)日：2000-07-11
申请号：US226748
申请日：1999-01-06
申请人： Eric N. Mann
发明人： Eric N. Mann
IPC分类号： G11C16/10 , G11C19/00
CPC分类号： G11C16/10 , G11C19/00
摘要： A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.
摘要翻译：使用单个引脚提供两个或更多个控制信号（例如，时钟和数据信号）的寄存器。本发明解码三态输入波形以产生时钟/写信号，并且使用三态时钟波形来产生时钟/读数据信号。本发明通常包括三电平接收器，锁存器和输出驱动器，以形成与移位寄存器一起使用的单引脚双向接口。要写入，接口将三电平输入信号转换为驱动移位寄存器的单独的时钟和数据信号。为了读取，接口将双电平输入信号转换为表示移位寄存器的输出的三电平输出信号。结果，本发明允许在时钟芯片中编程诸如可擦除可编程只读存储器（EPROM）的器件，同时利用最少数量的引脚。

3. 发明授权

US5881121A One-pin shift register interface 失效
公开(公告)号：US5881121A
公开(公告)日：1999-03-09
申请号：US799835
申请日：1997-02-13
申请人： Eric N. Mann
发明人： Eric N. Mann
IPC分类号： G11C16/10 , G11C19/00
CPC分类号： G11C16/10 , G11C19/00
摘要： A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

4. 发明授权

US06433645B1 Programmable clock generator 失效
标题翻译：可编程时钟发生器
公开(公告)号：US06433645B1
公开(公告)日：2002-08-13
申请号：US09048905
申请日：1998-03-26
申请人： Eric N. Mann , John Q. Torode
发明人： Eric N. Mann , John Q. Torode
IPC分类号： A03L700
CPC分类号： H03L7/07 , G06F1/08 , H03L7/183
摘要： A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.
摘要翻译：公开了一种用于产生时钟信号的可编程电路。本发明提供了一种时钟发生器架构，其将基于PLL的时钟发生器电路与片上EPROM组合在单片时钟发生器芯片中。时钟发生器允许电气配置各种信息，包括PLL参数，输入阈值，输出驱动电平和输出频率。可以在制造时钟发生器之后配置各种参数。参数可以在晶圆分类或包装后配置。时钟发生器可以在打包之前被擦除，从而可以验证编程。

5. 发明授权

US06175259B1 Clock generator with programmable two-tone modulation for EMI reduction 有权
标题翻译：具有可编程双音调制的时钟发生器，用于降低EMI
公开(公告)号：US06175259B1
公开(公告)日：2001-01-16
申请号：US09246981
申请日：1999-02-09
申请人： Eric N. Mann , Galen E. Stansell , Monte F. Mar
发明人： Eric N. Mann , Galen E. Stansell , Monte F. Mar
IPC分类号： H03L700
CPC分类号： H03L7/197
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为响应于（i）第一控制信号，（ii）第二控制信号和（iii）第一参考信号而产生在第一和第二频率之间斜坡的输出信号。第二电路可以被配置为响应于具有第三频率的第三控制信号来产生第一和第二控制信号。第三频率可以减小由第一电路产生的电磁干扰。

6. 发明授权

US5896069A Cross coupled differential oscillator 失效
标题翻译：交叉耦合差分振荡器
公开(公告)号：US5896069A
公开(公告)日：1999-04-20
申请号：US815701
申请日：1997-03-12
申请人： Bertrand J. Williams , Eric N. Mann
发明人： Bertrand J. Williams , Eric N. Mann
IPC分类号： H03K3/0231 , H03B5/02 , H03K3/354
CPC分类号： H03K3/0231
摘要： A multi-stage apparatus used as a voltage controlled oscillator. Each stage includes a first complementary differential current switch and a second complementary differential current switch with a second set of complementary differential current switches having a first complementary differential current switch and a second complementary differential current switch, the two sets of complementary differential current switches are connected in a push pull arrangement. In this arrangement, the outputs of the first complementary differential current switch of the first set of complementary differential current switches and the first complementary differential current switch of the second set of complementary differential current switches are connected with the input of the second complementary differential current switch of the first set of complementary differential current switches. The outputs of the second complementary differential current switch of the first set of complementary differential current switches and the second complementary differential current switch of the second set of complementary differential current switches are connected with the input of the first complementary differential current switch of the second set of complementary differential current switches. A controlled complementary voltage clamp is connected to the output nodes of the first set of complementary differential current switches and a controlled complementary voltage clamp is connected to the output nodes of the second set of complementary differential current switches.
摘要翻译：用作压控振荡器的多级装置。每个级包括第一互补差分电流开关和具有第二组互补差分电流开关的第二互补差分电流开关，其具有第一互补差分电流开关和第二互补差分电流开关，所述两组互补差分电流开关连接在推拉装置中。在这种布置中，第一组互补差动电流开关的第一互补差动电流开关和第二组互补差动电流开关的第一互补差动电流开关的输出与第二互补差动电流开关的第一组互补差动电流开关。第一组互补差分电流开关的第二互补差动电流开关和第二组互补差动电流开关的第二互补差动电流开关的输出与第二组的第一互补差动电流开关的输入相连接的互补差分电流开关。受控互补电压钳位电路连接到第一组互补差动电流开关的输出节点，受控互补电压钳位电路连接到第二组互补差动电流开关的输出节点。

7. 发明授权

US5764714A Latching inputs and enabling outputs on bidirectional pins with a phase locked loop (PLL) lock detect circuit 失效
标题翻译：使用锁相环（PLL）锁定检测电路在双向引脚上锁存输入和使能输出
公开(公告)号：US5764714A
公开(公告)日：1998-06-09
申请号：US700249
申请日：1996-08-20
申请人： Galen E. Stansell , J. Kenneth Fox , Eric N. Mann , James P. Myers , Timothy V. Wright
发明人： Galen E. Stansell , J. Kenneth Fox , Eric N. Mann , James P. Myers , Timothy V. Wright
IPC分类号： H03L7/07 , H03L7/089 , H03L7/095 , G06F13/00
CPC分类号： H03L7/095 , H03L7/07 , H03L7/089 , Y10S331/02
摘要： A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i.e., enable) the output signal to the bidirectional pin when the delayed lock control signal is active.
摘要翻译：公开了一种用于使用PLL锁定检测电路锁存输入和使能双向引脚的输出的电路。当输出参考信号相对于施加到锁相环（PLL）电路的输入参考信号相位锁定时，PLL锁定检测电路产生有效锁定控制信号。锁存器和使能电路响应于该锁定控制信号来锁存输入信号（引脚之外），然后使输出信号输出到双向引脚上。当锁定控制信号进入活动状态时，锁存器和使能电路包括数据锁存器以存储输入信号。锁存器和使能电路还包括延迟电路以延迟锁定控制信号以产生延迟的锁定控制信号，以及当延迟的锁定控制信号无效但被操作以通过时（即，使能）的三态输出驱动器）当延迟锁定控制信号有效时，输出信号到双向引脚。

8. 发明授权

US06956419B1 Fail-safe zero delay buffer with automatic internal reference 有权
标题翻译：具有自动内部参考值的故障安全零延迟缓冲器
公开(公告)号：US06956419B1
公开(公告)日：2005-10-18
申请号：US10833357
申请日：2004-04-28
申请人： Eric N. Mann , John J. Wunner
发明人： Eric N. Mann , John J. Wunner
IPC分类号： H03L7/087 , H03L7/089 , H03L7/099 , H03L7/23 , H03L7/00
CPC分类号： H03L7/23 , H03L7/087 , H03L7/089 , H03L7/099
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以包括控制电路和振荡器。控制电路可以被配置为响应于第一参考信号和第二参考信号而产生控制信号。振荡器可以被配置为响应于控制信号和定时信号而产生第二参考信号。当第一参考信号丢失时，控制信号通常被保持。第二电路可以被配置为响应于第二参考信号和一个或多个输出信号中的一个而产生一个或多个输出信号。一个或多个输出信号可以具有相对于第一参考信号的受控延迟。

9. 发明授权

US06768362B1 Fail-safe zero delay buffer with automatic internal reference 有权
标题翻译：具有自动内部参考值的故障安全零延迟缓冲器
公开(公告)号：US06768362B1
公开(公告)日：2004-07-27
申请号：US09928818
申请日：2001-08-13
申请人： Eric N. Mann , John J. Wunner
发明人： Eric N. Mann , John J. Wunner
IPC分类号： H03L700
CPC分类号： H03L7/23 , H03L7/087 , H03L7/089 , H03L7/099
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为接收第一参考信号并产生第二参考信号。第二参考信号的频率和相位可以（i）响应于第一参考信号而被调整，并且（ii）当第一参考信号丢失时保持。第二电路可以被配置为响应于第二参考信号和一个或多个输出信号中的一个而产生一个或多个输出信号。一个或多个输出信号可以相对于第一参考信号具有受控和/或基本为零的延迟。

10. 发明授权

US06388478B1 Configurable clock generator 有权
标题翻译：可配置时钟发生器
公开(公告)号：US06388478B1
公开(公告)日：2002-05-14
申请号：US09782482
申请日：2001-02-13
申请人： Eric N. Mann
发明人： Eric N. Mann
IPC分类号： H03K190175
CPC分类号： H03L7/07 , G06F1/08 , H03L7/0898 , H03L7/183
摘要： A circuit and method for implementing a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.
摘要翻译：一种用于实现可配置时钟发生器的电路和方法，包括逻辑电路，可配置矩阵和锁相环。逻辑电路可以被配置为产生多个控制信号。可配置矩阵可以包括多个互连，其可以被配置为（i）从逻辑电路接收多个控制信号，以及（ii）将控制信号汇总到锁相环。多个控制信号可以控制锁相环的操作。在一个示例中，逻辑电路可以包括大门逻辑阵列。

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