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1. 发明申请

US20080054326A1 LOW RESISTANCE CONTACT STRUCTURE AND FABRICATION THEREOF 有权
标题翻译：低电阻接触结构及其制造
公开(公告)号：US20080054326A1
公开(公告)日：2008-03-06
申请号：US11470349
申请日：2006-09-06
申请人： Keith Kwong Hon Wong , Patrick W. DeHaven , Sadanand V. Deshpande , Anita Madan
发明人： Keith Kwong Hon Wong , Patrick W. DeHaven , Sadanand V. Deshpande , Anita Madan
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/76846 , H01L21/76856
摘要： Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.
摘要翻译：本发明的实施例提供一种在半导体器件和后端串联之间的电介质材料层中制造接触结构的方法。该方法包括在所述介电材料层中形成至少一个接触开口; 通过化学气相沉积工艺形成第一TiN膜，所述第一TiN膜衬在所述接触开口上; 以及通过物理气相沉积工艺形成第二TiN膜，所述第二TiN膜衬在所述第一TiN膜上。还提供了根据本发明的实施例制造的接触结构。

2. 发明授权

US06960510B2 Method of making sub-lithographic features 失效
标题翻译：制作亚光刻特征的方法
公开(公告)号：US06960510B2
公开(公告)日：2005-11-01
申请号：US10187579
申请日：2002-07-01
申请人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
发明人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L21/033 , H01L21/265 , H01L21/28 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L21/26586 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L21/31144
摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.
摘要翻译：提供了形成具有亚光刻尺寸的结构的方法。该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

3. 发明授权

US07479688B2 STI stress modification by nitrogen plasma treatment for improving performance in small width devices 有权
标题翻译：通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能
公开(公告)号：US07479688B2
公开(公告)日：2009-01-20
申请号：US10751831
申请日：2004-01-05
申请人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
发明人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
IPC分类号： H01L29/72
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译：一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。在又一实施例中，等离子体氮化处理发生在沟槽填充之后。在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

4. 发明申请

US20090008785A1 ETCH PROCESS FOR IMPROVING YIELD OF DIELECTRIC CONTACTS ON NICKEL SILICIDES 审中-公开
标题翻译：用于改善镍基电介质接触电阻的ETCH工艺
公开(公告)号：US20090008785A1
公开(公告)日：2009-01-08
申请号：US12027407
申请日：2008-02-07
申请人： Scott D. ALLEN , Kenneth A. Bandy , Sadanand V. Deshpande , Richard Wise
发明人： Scott D. ALLEN , Kenneth A. Bandy , Sadanand V. Deshpande , Richard Wise
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/31116
摘要： The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device
摘要翻译：本发明的实施例通常涉及蚀刻工艺，更具体地涉及用于提高硅化镍上的电介质触点的产量的蚀刻处理。在蚀刻过程中使用无氧原料气，以减少或消除在接触表面处的残余物，包括硅化物层的氧化和消耗。接触表面的接触电阻降低，从而提高器件的性能

5. 发明授权

US07407875B2 Low resistance contact structure and fabrication thereof 有权
标题翻译：低电阻接触结构及其制造
公开(公告)号：US07407875B2
公开(公告)日：2008-08-05
申请号：US11470349
申请日：2006-09-06
申请人： Keith Kwong Hon Wong , Patrick W. DeHaven , Sadanand V. Deshpande , Anita Madan
发明人： Keith Kwong Hon Wong , Patrick W. DeHaven , Sadanand V. Deshpande , Anita Madan
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L21/76846 , H01L21/76856
摘要： Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.
摘要翻译：本发明的实施例提供一种在半导体器件和后端串联之间的电介质材料层中制造接触结构的方法。该方法包括在所述介电材料层中形成至少一个接触开口; 通过化学气相沉积工艺形成第一TiN膜，所述第一TiN膜衬在所述接触开口上; 以及通过物理气相沉积工艺形成第二TiN膜，所述第二TiN膜衬在所述第一TiN膜上。还提供了根据本发明的实施例制造的接触结构。

6. 发明授权

US07361611B2 Doped nitride film, doped oxide film and other doped films 有权
标题翻译：掺杂氮化物膜，掺杂氧化物膜等掺杂膜
公开(公告)号：US07361611B2
公开(公告)日：2008-04-22
申请号：US11349233
申请日：2006-02-08
申请人： Ashima B. Chakravarti , Judson Holt , Kevin K. Chan , Sadanand V. Deshpande , Rangarajan Jagannathan
发明人： Ashima B. Chakravarti , Judson Holt , Kevin K. Chan , Sadanand V. Deshpande , Rangarajan Jagannathan
IPC分类号： H01L21/31
CPC分类号： H01L29/7843 , C23C16/308 , C23C16/34 , C23C16/401 , H01L21/0214 , H01L21/0217 , H01L21/02271 , H01L21/3143 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31612 , H01L21/3185 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L29/7833 , H01L29/78675
摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.
摘要翻译：在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能的电影，如调整电影的压力。此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

7. 发明授权

US06884734B2 Vapor phase etch trim structure with top etch blocking layer 失效
标题翻译：具有顶部蚀刻阻挡层的气相蚀刻修整结构
公开(公告)号：US06884734B2
公开(公告)日：2005-04-26
申请号：US09989822
申请日：2001-11-20
申请人： Frederick W. Buehrer , Derek Chen , William Chu , Scott Crowder , Sadanand V. Deshpande , David V. Horak , Wesley C. Natzle , Hung Y. Ng , Len Y. Tsou , Chienfan Yu
发明人： Frederick W. Buehrer , Derek Chen , William Chu , Scott Crowder , Sadanand V. Deshpande , David V. Horak , Wesley C. Natzle , Hung Y. Ng , Len Y. Tsou , Chienfan Yu
IPC分类号： H01L21/033 , H01L21/28 , H01L21/302 , H01L21/3205 , H01L21/3213 , H01L21/461 , H01L21/8234
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28123
摘要： A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.
摘要翻译：在具有初始厚度的硬掩模上形成阻挡层。线通过图案化阻挡层和硬掩模来制造以提供线段，线段具有跨越线段测量的第一尺寸; 使所述线段的表面层反应以在所述线段的剩余部分上形成反应产物层; 并且除去反应产物而不攻击线段的剩余部分，而不攻击阻挡层和基底，以形成跨越比第一尺寸小的线段的具有第二尺寸的线段。阻挡层防止在硬掩模上形成反应产物，从而保持硬掩模的初始厚度。阻挡层也可以用作光致抗蚀剂图案化的ARC层，从而不需要使用附加的膜层。

8. 发明授权

US07595010B2 Method for producing a doped nitride film, doped oxide film and other doped films 有权
标题翻译：用于制造掺杂氮化物膜，掺杂氧化物膜和其它掺杂膜的方法
公开(公告)号：US07595010B2
公开(公告)日：2009-09-29
申请号：US11924825
申请日：2007-10-26
申请人： Ashima B. Chakravarti , Judson Holt , Kevin K. Chan , Sadanand V. Deshpande , Rangarajan Jagannathan
发明人： Ashima B. Chakravarti , Judson Holt , Kevin K. Chan , Sadanand V. Deshpande , Rangarajan Jagannathan
IPC分类号： H01B1/00
CPC分类号： H01L29/7843 , C23C16/308 , C23C16/34 , C23C16/401 , H01L21/0214 , H01L21/0217 , H01L21/02271 , H01L21/3143 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31612 , H01L21/3185 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L29/7833 , H01L29/78675
摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.
摘要翻译：在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能的电影，如调整电影的压力。此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

9. 发明授权

US07091081B2 Method for patterning a semiconductor region 失效
标题翻译：图案化半导体区域的方法
公开(公告)号：US07091081B2
公开(公告)日：2006-08-15
申请号：US10709673
申请日：2004-05-21
申请人： Sadanand V. Deshpande , Rajiv M. Ranade , George K. Worth
发明人： Sadanand V. Deshpande , Rajiv M. Ranade , George K. Worth
IPC分类号： H01L21/8238
CPC分类号： H01L21/28035 , H01L21/32137 , H01L29/4925
摘要： A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.
摘要翻译：提供了可以重掺杂的半导体区域图形化的方法。在半导体区域上方设置图案化掩模。通过图案化掩模曝光的半导体区域的一部分在包括聚合碳氟化合物，例如碳与氟原子比高的无氯碳氟化合物的环境中被蚀刻，以及至少一种选自下组的非聚合物质由非聚合碳氟化合物组成，例如碳与氟原子比低的氢化碳氟化合物。该方法优选地钝化图案化的半导体区域的侧壁，使得可以在图案化区域下方的半导体材料的下部区域被定向蚀刻，而不会侵蚀如此钝化的图案化区域。

10. 发明授权

US06930030B2 Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness 失效
标题翻译：在硅的薄膜的表面上的凹部上形成电子器件的方法被蚀刻到精确的厚度
公开(公告)号：US06930030B2
公开(公告)日：2005-08-16
申请号：US10453080
申请日：2003-06-03
申请人： Werner A. Rausch , Tina J. Wagner , Sadanand V. Deshpande
发明人： Werner A. Rausch , Tina J. Wagner , Sadanand V. Deshpande
IPC分类号： H01L21/265 , H01L21/28 , H01L21/3065 , H01L21/3213 , H01L21/336 , H01L29/78 , H01L21/3205 , H01L21/302
CPC分类号： H01L29/66621 , H01L21/26506 , H01L21/2658 , H01L21/28114 , H01L21/3065 , H01L21/32137 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/7834
摘要： A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask. In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.
摘要翻译：用于精确稀化以在晶体硅层中形成精确深度的凹槽的方法，其可用于形成诸如MOSFET器件的各种器件，包括以下步骤。在硅层的顶表面上形成具有窗口的图案掩模。在窗口下方的硅层的顶表面形成非晶化区域。选择性地蚀刻去除硅层的非晶化区域，以在硅层表面形成凹陷，并去除图形掩模。在MOSFET器件的情况下，在图案掩模下形成硬掩模，窗口延伸穿过其中。然后通过硬掩模在窗口中产生侧壁间隔物，并在窗口中形成栅极电极堆叠。然后去除硬掩模，形成源极/漏极延伸部分，光晕和区域加上硅化物，并完成MOSFET器件。

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