专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5851928A Method of etching a semiconductor substrate 失效
标题翻译：蚀刻半导体衬底的方法
公开(公告)号：US5851928A
公开(公告)日：1998-12-22
申请号：US562865
申请日：1995-11-27
申请人： Jerry D. Cripe , Jerry L. White , Carl E. D'Acosta
发明人： Jerry D. Cripe , Jerry L. White , Carl E. D'Acosta
IPC分类号： H01L21/301 , H01L21/306 , H01L21/308 , H01L21/302
CPC分类号： H01L21/30608 , H01L21/3081
摘要： A method of etching a semiconductor substrate (11) includes thinning (102) the semiconductor substrate (11), providing (103) a support layer (30) for the semiconductor substrate (11), providing (104) an etch mask (28) over the semiconductor substrate (11), and etching (105) the semiconductor substrate (11) using an etchant mixture of hydrofluoric acid, nitric acid, phosphoric acid, sulfuric acid, and a wetting agent at a temperature below ambient. The method is capable of using one etch step (105) and one etch mask (28) to form a plurality of trenches (12, 13) having the same width (15, 17) but different depths (16, 18) and different orientations. The method can be used to singulate different sizes and configurations of semiconductor dice from the semiconductor substrate (11).
摘要翻译：蚀刻半导体衬底（11）的方法包括使半导体衬底（11）变薄（102），提供（103）用于半导体衬底（11）的支撑层（30），提供（104）蚀刻掩模（28）并且在低于环境温度的温度下使用氢氟酸，硝酸，磷酸，硫酸和润湿剂的蚀刻剂混合物蚀刻（105）半导体衬底（105）。该方法能够使用一个蚀刻步骤（105）和一个蚀刻掩模（28）形成具有相同宽度（15,17）但不同深度（16,18）和不同取向的多个沟槽（12,13）。该方法可用于从半导体衬底（11）中分离出不同尺寸和结构的半导体晶片。

2. 发明授权

US07444012B2 Method and apparatus for performing failure analysis with fluorescence inks 有权
标题翻译：用荧光油墨进行故障分析的方法和装置
公开(公告)号：US07444012B2
公开(公告)日：2008-10-28
申请号：US10626781
申请日：2003-07-24
申请人： Jerry L. White , Russell T. Lee
发明人： Jerry L. White , Russell T. Lee
IPC分类号： G06K9/00
CPC分类号： G01N21/91
摘要： A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device sample possibly including a failure area having wicked in encapsulation material containing the dye. The prepared device sample is then sectioned to facilitate viewing a cross section face of the device under inspection. Lastly, a dark field analysis on the prepared device sample is performed with the use of dark field illumination. Responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained.
摘要翻译：在检查的半导体器件上执行故障分析的方法包括使用包含染料的封装材料来制备器件样品，所制备的器件样品可能包括在包含染料的包封材料中具有恶性的破坏区域。然后将准备好的装置样品切片以便于观察被检查装置的横截面。最后，使用暗场照明进行对制备的器件样品的暗场分析。响应于在被检测装置的截面上出现染料的包封材料中含有邪恶的至少一个故障区域，可以容易地识别故障区域以及保持截面的剩余部分的对比度和透视图。

3. 发明授权

US5221639A Method of fabricating resistive conductive patterns on aluminum nitride substrates 失效
标题翻译：在氮化铝衬底上制作电阻导电图案的方法
公开(公告)号：US5221639A
公开(公告)日：1993-06-22
申请号：US811272
申请日：1991-10-20
申请人： Jerry L. White
发明人： Jerry L. White
IPC分类号： H01L23/15 , H01L21/48 , H01L21/70 , H01L23/498 , H01L23/66 , H05K1/03 , H05K1/16 , H05K3/38
CPC分类号： H01L23/66 , H01L21/4846 , H01L21/707 , H01L23/49866 , H01L2924/0002 , H05K1/0306 , H05K1/167 , H05K3/38 , Y10T29/4913
摘要： A method of fabricating a resistive conductive pattern on an aluminum nitride substrate includes forming a resistive chromium containing film on the aluminum nitride substrate and then forming a refractory metal layer on the resistive film. The resistive film and refractory metal layer are then patterned and one or more conductive layers may then be formed on the patterned refractory metal layer. Resistors may then be formed between conductive lines patterned from the layers. These resistors are formed from the resistive film.

4. 发明授权

US4297860A Device for applying foam to textiles 失效
标题翻译：将泡沫应用于纺织品的装置
公开(公告)号：US4297860A
公开(公告)日：1981-11-03
申请号：US171277
申请日：1980-07-23
申请人： Joseph A. Pacifici , Jerry L. White
发明人： Joseph A. Pacifici , Jerry L. White
IPC分类号： B29C44/34 , B29C44/46 , D06B19/00 , D06B1/08
CPC分类号： D06B19/0094 , B29C44/3473 , B29C44/461 , Y10S68/90
摘要： Metered amounts of air and liquid are mixed to produce a foam which is directed to an applicator. The applicator includes an apertured spreading plate, a bed of porous material, and a contour which converges towards a discharge orifice to uniformly distribute the foam across the orifice.
摘要翻译：将计量的空气和液体混合以产生被引导至施加器的泡沫。施加器包括有孔扩散板，多孔材料床和朝向排放孔会聚的轮廓，以均匀地分布泡沫穿过孔口。

5. 发明申请

US20080182363A1 METHOD FOR FORMING A MICROELECTRONIC ASSEMBLY INCLUDING ENCAPSULATING A DIE USING A SACRIFICIAL LAYER 审中-公开
标题翻译：形成微电子组件的方法，其中包括使用真空层进行封装
公开(公告)号：US20080182363A1
公开(公告)日：2008-07-31
申请号：US11669625
申请日：2007-01-31
申请人： Craig S. Amrine , Owen R. Fay , Lizabeth Ann Keser , Kevin R. Lish , William H. Lytle , Chandrasekaram Ramiah , Jerry L. White
发明人： Craig S. Amrine , Owen R. Fay , Lizabeth Ann Keser , Kevin R. Lish , William H. Lytle , Chandrasekaram Ramiah , Jerry L. White
IPC分类号： H01L21/56
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/10329 , H01L2924/14 , H01L2924/15174 , H01L2924/15311
摘要： A method for forming a microelectronic assembly is provided. A carrier substrate (30) is provided. A sacrificial layer (38) is formed over the carrier substrate. A polymeric layer (40), including a polymeric tape (42) and a polymeric layer adhesive (44), is formed over the sacrificial layer. The polymeric layer adhesive is between the sacrificial layer and the polymeric tape. A microelectronic die (52), having an integrated circuit formed therein, is placed on the polymeric layer. The microelectronic die is encapsulated with an encapsulation material (54) to form an encapsulated structure (58). The polymeric layer and the encapsulated structure are separated from the carrier substrate. The separating of the polymeric layer and the encapsulated structure includes at least partially deteriorating the sacrificial layer.
摘要翻译：提供一种用于形成微电子组件的方法。提供载体基板（30）。牺牲层（38）形成在载体衬底上。在牺牲层之上形成包括聚合物带（42）和聚合物层粘合剂（44）的聚合物层（40）。聚合物层粘合剂在牺牲层和聚合物带之间。在其上形成有集成电路的微电子管芯（52）放置在聚合物层上。微电子管芯用封装材料（54）封装以形成封装结构（58）。聚合物层和封装结构与载体基质分离。聚合物层和封装结构的分离包括至少部分地使牺牲层劣化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式