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1. 发明授权

US07444012B2 Method and apparatus for performing failure analysis with fluorescence inks 有权
标题翻译：用荧光油墨进行故障分析的方法和装置
公开(公告)号：US07444012B2
公开(公告)日：2008-10-28
申请号：US10626781
申请日：2003-07-24
申请人： Jerry L. White , Russell T. Lee
发明人： Jerry L. White , Russell T. Lee
IPC分类号： G06K9/00
CPC分类号： G01N21/91
摘要： A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device sample possibly including a failure area having wicked in encapsulation material containing the dye. The prepared device sample is then sectioned to facilitate viewing a cross section face of the device under inspection. Lastly, a dark field analysis on the prepared device sample is performed with the use of dark field illumination. Responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained.
摘要翻译：在检查的半导体器件上执行故障分析的方法包括使用包含染料的封装材料来制备器件样品，所制备的器件样品可能包括在包含染料的包封材料中具有恶性的破坏区域。然后将准备好的装置样品切片以便于观察被检查装置的横截面。最后，使用暗场照明进行对制备的器件样品的暗场分析。响应于在被检测装置的截面上出现染料的包封材料中含有邪恶的至少一个故障区域，可以容易地识别故障区域以及保持截面的剩余部分的对比度和透视图。

2. 发明授权

US5346857A Method for forming a flip-chip bond from a gold-tin eutectic 失效
标题翻译：从金锡共晶形成倒装芯片焊接的方法
公开(公告)号：US5346857A
公开(公告)日：1994-09-13
申请号：US952005
申请日：1992-09-28
申请人： Thomas A. Scharr , Russell T. Lee , Ravichandran Subrahmanyan
发明人： Thomas A. Scharr , Russell T. Lee , Ravichandran Subrahmanyan
IPC分类号： H01L21/60 , H01L21/283 , H01L21/58 , H01L21/603
CPC分类号： H01L24/81 , H01L24/75 , H01L2224/13144 , H01L2224/16 , H01L2224/75 , H01L2224/75283 , H01L2224/8123 , H01L2224/81801 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/14
摘要： A method for flip-chip bonding an integrated circuit die to a substrate. A substrate (21) having conductive bonding areas (22) coated with tin (23) is secured to a bottom end effector of a flip-chip bonding apparatus. An integrated circuit die (26) having gold bumps (28) is secured to a die tool of the flip-chip bonding apparatus. A gold-tin eutectic bond is formed between the integrated circuit die (26) and the conductive bonding areas (22) of the substrate (21).
摘要翻译：一种用于将集成电路管芯倒装连接到衬底的方法。具有涂覆有锡（23）的导电接合区域（22）的基板（21）固定到倒装芯片接合装置的底端执行器。具有金凸块（28）的集成电路芯片（26）固定到倒装芯片接合装置的模具工具。在集成电路管芯（26）和衬底（21）的导电接合区域（22）之间形成金锡共晶键。

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