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1. 发明申请

US20090040824A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090040824A1
公开(公告)日：2009-02-12
申请号：US12187678
申请日：2008-08-07
申请人： Hirohisa IIZUKA
发明人： Hirohisa IIZUKA
IPC分类号： G11C16/04 , G11C7/00 , G11C5/02 , H01L21/82
CPC分类号： H01L27/115 , G11C5/063 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a plurality of a word lines. The word lines have a set of odd word lines and a set of even word lines. The odd and the even word lines are located from a first end region to a second end region through the cell region located between the first and the second end regions. The odd word lines are divided in the first end region and the even word lines are divided in the second end region to form dummy word line portions.
摘要翻译：半导体器件包括多个字线。字线具有一组奇数字线和一组偶数字线。奇数和偶数字线通过位于第一和第二端部区域之间的单元区域从第一端部区域到第二端部区域。奇数字线在第一端区域中分割，并且偶数字线在第二端区域中分割以形成伪字线部分。

2. 发明申请

US20070190727A1 Nonvolatile semiconductor memory device and manufacturing method therefor 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070190727A1
公开(公告)日：2007-08-16
申请号：US11783368
申请日：2007-04-09
申请人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
发明人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7881
摘要： A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.
摘要翻译：一种制造在外围电路中包括至少一个MOS晶体管的非易失性半导体存储器件的方法，还包括在半导体衬底中形成用于存储单元的第一阱和用于MOS晶体管的第二阱。

3. 发明授权

US06828648B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06828648B2
公开(公告)日：2004-12-07
申请号：US10655122
申请日：2003-09-04
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L2900
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

4. 发明授权

US06747311B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06747311B2
公开(公告)日：2004-06-08
申请号：US10145122
申请日：2002-05-15
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A nonvolatile semiconductor memory device includes memory cell transistors, peripheral transistors, first post-oxidation films provided on the gate electrode of all of the memory cell transistors, second post-oxidation films provided on the gate electrode of all of the peripheral transistors, first insulating films provided on the first post-oxidation films and covering a side surface of the gate electrode of all of the memory cell transistors and second insulating films provided on the second post-oxidation films and covering a side surface of the gate electrode of all of the peripheral transistors. The first and second insulating films are harder for an oxidizing agent to pass therethrough than a silicon oxide film, and the first and second insulating films are oxidized.
摘要翻译：非易失性半导体存储器件包括存储单元晶体管，外围晶体管，设置在所有存储单元晶体管的栅电极上的第一后氧化膜，设置在所有外围晶体管的栅电极上的第二后氧化膜，第一绝缘提供在第一后氧化膜上并覆盖所有存储单元晶体管的栅电极的侧表面的膜和设置在第二后氧化膜上的第二绝缘膜，并覆盖所有栅极电极的侧表面外围晶体管。第一绝缘膜和第二绝缘膜比氧化硅膜更难以通过氧化剂，并且第一和第二绝缘膜被氧化。

5. 发明授权

US06413809B2 Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench 失效
标题翻译：制造具有嵌入在沟槽中的元件隔离绝缘膜的非易失性存储器的方法
公开(公告)号：US06413809B2
公开(公告)日：2002-07-02
申请号：US09800914
申请日：2001-03-08
申请人： Takuya Nakamura , Naoki Koido , Hirohisa Iizuka , Kazuhito Narita , Seiichi Aritome , Fumitaka Arai
发明人： Takuya Nakamura , Naoki Koido , Hirohisa Iizuka , Kazuhito Narita , Seiichi Aritome , Fumitaka Arai
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
摘要翻译：半导体器件具有半导体衬底，在从所述半导体衬底的表面突出的状态下嵌入形成在所述半导体衬底中的沟槽中的元件隔离绝缘膜和设置在由所述元件隔离包围的区域中的栅电极的晶体管绝缘膜，并且包含在嵌入所述元件隔离绝缘膜之前通过栅极绝缘膜沉积的栅电极，并且所述元件隔离绝缘膜的上边缘角被选择性地凹入。在这样构成的半导体器件中，元件隔离绝缘膜的上边缘角在栅电极的图案化处理之前是凹进的，从而防止了在栅电极的图案化处理中栅电极的一部分未被蚀刻的情况。

6. 发明授权

US06288942B1 Nonvolatile semiconductor storage device and its manufacturing method 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06288942B1
公开(公告)日：2001-09-11
申请号：US09632626
申请日：2000-08-04
申请人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
发明人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.
摘要翻译：用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置多个NAND存储器单元。用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。

7. 发明授权

US07297599B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07297599B2
公开(公告)日：2007-11-20
申请号：US11219752
申请日：2005-09-07
申请人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
发明人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
IPC分类号： H01L21/8234
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅电极，栅极绝缘膜插入在衬底和电极之间，形成用于元件隔离的绝缘膜，从半导体衬底的表面突出，形成氧化膜在已经形成有栅电极和元件隔离绝缘膜的半导体衬底的表面上，在使用用于去除氧化膜的抗蚀剂图案的同时，在要形成自对准接触孔的区域中除去氧化膜形成在其中形成自对准接触孔的区域中，并且蚀刻从半导体衬底的表面突出的元件隔离绝缘膜的一部分，使得所述部分基本上与半导体衬底的表面成一定水平，同时使用抗蚀剂图案去除形成在自对准接触区域中的氧化膜形成孔。

8. 发明申请

US20050253202A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050253202A1
公开(公告)日：2005-11-17
申请号：US11126285
申请日：2005-05-11
申请人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
发明人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/04 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76897 , H01L21/26586 , H01L21/76802 , H01L21/76834 , H01L27/10873 , H01L27/10894
摘要： A semiconductor device includes a semiconductor substrate, a plurality of memory cell transistors and select gate transistors both formed in a memory cell region of the semiconductor substrate, and a transistor formed in a peripheral circuit region of the substrate and having a high breakdown voltage. Each select gate transistor of the memory cell region has a gate electrode under which an ion implanted layer is formed for adjustment of a threshold. The transistor having the high breakdown voltage includes a contact region around which a gate insulation film remains.
摘要翻译：半导体器件包括形成在半导体衬底的存储单元区域中的半导体衬底，多个存储单元晶体管和选择栅极晶体管，以及形成在衬底的外围电路区域中且具有高击穿电压的晶体管。存储单元区域的每个选择栅极晶体管具有栅电极，在该栅电极处形成用于调整阈值的离子注入层。具有高击穿电压的晶体管包括保持栅极绝缘膜的接触区域。

9. 发明授权

US06828627B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06828627B2
公开(公告)日：2004-12-07
申请号：US10742952
申请日：2003-12-23
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

10. 发明授权

US06703669B1 Semiconductor device having serially connected memory cell transistors provided between two current terminals 有权
标题翻译：具有串联连接的存储单元晶体管的半导体器件设置在两个电流端子之间
公开(公告)号：US06703669B1
公开(公告)日：2004-03-09
申请号：US09714228
申请日：2000-11-17
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

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