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1. 发明申请

US20060051908A1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060051908A1
公开(公告)日：2006-03-09
申请号：US11219752
申请日：2005-09-07
申请人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
发明人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
IPC分类号： H01L21/84
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅电极，栅极绝缘膜插入在衬底和电极之间，形成用于元件隔离的绝缘膜，从半导体衬底的表面突出，形成氧化膜在已经形成有栅电极和元件隔离绝缘膜的半导体衬底的表面上，在使用用于去除氧化膜的抗蚀剂图案的同时，在要形成自对准接触孔的区域中除去氧化膜形成在其中形成自对准接触孔的区域中，并且蚀刻从半导体衬底的表面突出的元件隔离绝缘膜的一部分，使得所述部分基本上与半导体衬底的表面成一定水平，同时使用抗蚀剂图案去除形成在自对准接触区域中的氧化膜形成孔。

2. 发明授权

US07297599B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07297599B2
公开(公告)日：2007-11-20
申请号：US11219752
申请日：2005-09-07
申请人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
发明人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
IPC分类号： H01L21/8234
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅电极，栅极绝缘膜插入在衬底和电极之间，形成用于元件隔离的绝缘膜，从半导体衬底的表面突出，形成氧化膜在已经形成有栅电极和元件隔离绝缘膜的半导体衬底的表面上，在使用用于去除氧化膜的抗蚀剂图案的同时，在要形成自对准接触孔的区域中除去氧化膜形成在其中形成自对准接触孔的区域中，并且蚀刻从半导体衬底的表面突出的元件隔离绝缘膜的一部分，使得所述部分基本上与半导体衬底的表面成一定水平，同时使用抗蚀剂图案去除形成在自对准接触区域中的氧化膜形成孔。

3. 发明申请

US20050253202A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050253202A1
公开(公告)日：2005-11-17
申请号：US11126285
申请日：2005-05-11
申请人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
发明人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/04 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76897 , H01L21/26586 , H01L21/76802 , H01L21/76834 , H01L27/10873 , H01L27/10894
摘要： A semiconductor device includes a semiconductor substrate, a plurality of memory cell transistors and select gate transistors both formed in a memory cell region of the semiconductor substrate, and a transistor formed in a peripheral circuit region of the substrate and having a high breakdown voltage. Each select gate transistor of the memory cell region has a gate electrode under which an ion implanted layer is formed for adjustment of a threshold. The transistor having the high breakdown voltage includes a contact region around which a gate insulation film remains.
摘要翻译：半导体器件包括形成在半导体衬底的存储单元区域中的半导体衬底，多个存储单元晶体管和选择栅极晶体管，以及形成在衬底的外围电路区域中且具有高击穿电压的晶体管。存储单元区域的每个选择栅极晶体管具有栅电极，在该栅电极处形成用于调整阈值的离子注入层。具有高击穿电压的晶体管包括保持栅极绝缘膜的接触区域。

4. 发明授权

US07195968B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07195968B2
公开(公告)日：2007-03-27
申请号：US11126285
申请日：2005-05-11
申请人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
发明人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/26586 , H01L21/76802 , H01L21/76834 , H01L27/10873 , H01L27/10894
摘要： A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting threshold-adjusting ions under the select gate with the resist pattern serving as a mask and removing an oxide film, forming a nitride film and an interlayer insulation film after the resist pattern has been removed, forming a resist pattern used to form a contact hole between the select gates and a contact hole for a transistor to be formed in the peripheral circuit region, the transistor having a higher breakdown voltage than a memory cell transistor and etching the interlayer insulation film, the nitride film and the gate insulation film individually with the resist pattern serving as a mask.
摘要翻译：一种制造半导体器件的方法包括形成抗蚀剂图案，使得选择栅极晶体管的选择栅极之间的开口形成在存储单元区域中，在选择栅极下方以阈值调节离子注入抗蚀图案作为掩模，去除氧化膜，在除去抗蚀剂图案之后形成氮化物膜和层间绝缘膜，形成用于在选择栅极之间形成接触孔的抗蚀剂图案和用于形成在外围电路中的晶体管的接触孔晶体管具有比存储单元晶体管更高的击穿电压，并且以抗蚀剂图案作为掩模分别蚀刻层间绝缘膜，氮化物膜和栅极绝缘膜。

5. 发明申请

US20060017111A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060017111A1
公开(公告)日：2006-01-26
申请号：US11186896
申请日：2005-07-22
申请人： Eiji Kamiya , Hiroaki Hazama , Tooru Hara
发明人： Eiji Kamiya , Hiroaki Hazama , Tooru Hara
IPC分类号： H01L29/94 , H01L23/52
CPC分类号： H01L21/76834 , H01L21/76802 , H01L21/76832 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, an interlayer insulating film formed so that the gate electrode is buried therein, a contact hole formed in the interlayer insulating film so as to be adjacent to the gate electrode, the contact hole having a sidewall, a nitride film for the spacer formed on the sidewall of the contact hole and having a lower end, an insulating film interposed between the lower end of the spacer nitride film and a surface of the semiconductor substrate, and a conductor layer for the electrode formed so as to fill the contact hole.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成为使得栅电极被埋入其中的层间绝缘膜，形成在层间绝缘层中的接触孔膜，以与栅电极相邻，接触孔具有侧壁，用于间隔物的氮化物膜形成在接触孔的侧壁上并具有下端，绝缘膜介于间隔氮化物的下端之间膜和半导体衬底的表面，以及形成为填充接触孔的用于电极的导体层。

6. 发明授权

US07432154B2 Non-volatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07432154B2
公开(公告)日：2008-10-07
申请号：US11733993
申请日：2007-04-11
申请人： Eiji Kamiya
发明人： Eiji Kamiya
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的存储单元阵列，并且包括具有第一厚度的第一栅极绝缘体。该器件还包括形成在半导体衬底上的高电压晶体管电路，并且包括具有大于第一厚度的第二厚度的第二栅极绝缘体，以及形成在半导体衬底上并包括第二栅极绝缘体的外围电路。

7. 发明授权

US06943074B2 Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same 失效
标题翻译：具有双层栅极结构的非易失性半导体存储器件及其制造方法
公开(公告)号：US06943074B2
公开(公告)日：2005-09-13
申请号：US10412365
申请日：2003-04-14
申请人： Eiji Kamiya , Kazuhiro Shimizu
发明人： Eiji Kamiya , Kazuhiro Shimizu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： In a memory cell, a gate oxide film is formed on a surface of semiconductor substrate and a first floating gate is formed on the gate oxide film. An insulating film is formed on a first floating gate and a second floating gate is formed on the insulating film. The first and second floating gates constitute a floating gate in the memory cell. An insulating film between the first floating gate and the second floating gate acts as an etching stopper when a polysilicon constituting the second floating gate is etched.
摘要翻译：在存储单元中，在半导体衬底的表面上形成栅极氧化膜，在栅氧化膜上形成第一浮栅。在第一浮栅上形成绝缘膜，在绝缘膜上形成第二浮栅。第一和第二浮动栅极构成存储单元中的浮动栅极。当构成第二浮栅的多晶硅被蚀刻时，第一浮栅和第二浮栅之间的绝缘膜用作蚀刻阻挡层。

8. 发明授权

US08674431B2 Non-volatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08674431B2
公开(公告)日：2014-03-18
申请号：US13399635
申请日：2012-02-17
申请人： Eiji Kamiya
发明人： Eiji Kamiya
IPC分类号： H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.
摘要翻译：一种制造非易失性半导体存储器件的方法，包括预先在半导体衬底上的第一周边区域中形成凹陷，在凹部中形成具有第一厚度的第一栅极绝缘体，形成第二厚度小于阵列区域中的第一厚度和半导体衬底上的第二周边区域，在第一和第二栅极绝缘体的每一个上依次沉积第一和第二栅电极膜以及第一和第二掩模绝缘体，在第一和第二栅极绝缘体的表面上形成隔离沟槽半导体衬底对应于阵列区域与周边区域的第一和第二区域之间的每个位置，在整个表面上沉积埋置的绝缘体，并且对掩埋绝缘体的上表面进行抛光，使得上表面可以被平坦化。

9. 发明授权

US07297594B2 Non-volatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07297594B2
公开(公告)日：2007-11-20
申请号：US11083930
申请日：2005-03-21
申请人： Eiji Kamiya
发明人： Eiji Kamiya
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的存储单元阵列，并且包括具有第一厚度的第一栅极绝缘体。该器件还包括形成在半导体衬底上的高压晶体管电路，并且包括具有大于第一厚度的第二厚度的第二栅极绝缘体，以及形成在半导体衬底上并包括第二栅极绝缘体的外围电路。

10. 发明授权

US6080624A Nonvolatile semiconductor memory and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US6080624A
公开(公告)日：2000-06-27
申请号：US104622
申请日：1998-06-25
申请人： Eiji Kamiya , Seiichi Aritome
发明人： Eiji Kamiya , Seiichi Aritome
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention is directed to a flash EEPROM in which a plurality of resist patterns are arranged like an island such that only an interlayer insulation film formed on a field oxide film is left in order to insulate drain diffusion layers of cell transistors in the row direction from each other when contacts of a memory cell group are subjected to PEP. Using the island-like resist patterns as masks, contact holes communicating with both the drain diffusion layers and source diffusion layers are made. Since, therefore, drain and source contact holes are arranged in matrix, the PEP margin can greatly be increased, thereby making it possible to prevent the problems of forming no contact holes and causing a short circuit between the gate and contact from arising.
摘要翻译：本发明涉及一种闪存EEPROM，其中多个抗蚀剂图案被布置成岛状，使得仅留下形成在场氧化膜上的层间绝缘膜，以便在行方向上使单元晶体管的漏极扩散层绝缘当存储单元组的接触受到PEP时，彼此之间。使用岛状抗蚀剂图案作为掩模，制成与漏极扩散层和源极扩散层相通的接触孔。因此，由于漏极和源极接触孔以矩阵形式布置，因此可以大大增加PEP余量，从而可以防止形成无接触孔并导致栅极和触点之间的短路的问题。

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