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1. 发明公开

KR1020120091787A 데이터 샘플링 장치 및 이를 이용한 데이터 샘플링 방법 有权
标题翻译：数据采样装置和数据采样方法
公开(公告)号：KR1020120091787A
公开(公告)日：2012-08-20
申请号：KR1020110011779
申请日：2011-02-10
申请人： 고려대학교 산학협력단
发明人： 김철우 , 곽영호 , 김경민
IPC分类号： H03K5/22 , H03K19/0175
CPC分类号： H03K5/24 , G11C27/02 , H03K5/153
摘要： PURPOSE: A data sampling apparatus and a data sampling method using the same are provided to prevent the generation of a plurality of parasitic components by simplifying the structure of a circuit. CONSTITUTION: Data sampling apparatus(100) comprises an inverter module(110) and sample and hold modules(130,140) connected to an input terminal of the inverter module. The inverter module includes inverters(112,114) having inputs and outputs which are crossly connected and a third switch(109) which connects or disconnects a first node and a second node of the inverter which is crossly connected according to the control of clock signals. The inverter module further includes a clock generation part generating the clock signals.
摘要翻译：目的：提供数据采样装置和使用其的数据采样方法，以通过简化电路的结构来防止产生多个寄生分量。构成：数据取样装置（100）包括与逆变器模块的输入端子连接的逆变器模块（110）和采样保持模块（130,140）。逆变器模块包括具有交叉连接的输入和输出的反相器（112,114）和连接或断开根据时钟信号的控制交叉连接的逆变器的第一节点和第二节点的第三开关（109）。逆变器模块还包括产生时钟信号的时钟产生部件。

2. 发明授权

KR100356074B1 저 소비전력으로 2진 논리신호를 전송하는 인터페이스 회로 및 방법 失效
标题翻译： 저소비전력으로2진논리신호를전송하는인터페이스회로및방저
公开(公告)号：KR100356074B1
公开(公告)日：2003-03-15
申请号：KR1019970025224
申请日：1997-06-17
申请人： 오끼 덴끼 고오교 가부시끼가이샤
发明人： 도미따다까시
IPC分类号： G06F13/14
CPC分类号： H04L25/0292 , H03K5/153 , H03K19/0175 , H04L25/0278 , H04L25/029
摘要： An interface circuit and method for transmitting a binary logic signal from a first electronic circuit to a second electronic circuit over a transmission line coupled to said first electronic circuit by a first terminal and to said second electronic circuit by a second terminal. The interface circuit transmits the binary logic signal by transmitting a pulse at a first potential at each falling transition of the binary logic signal, and a pulse at a second potential at each rising transition of the binary logic signal. At other times, the output terminal of a driver circuit is placed in a high-impedance state. A receiver circuit outputs a first logic Level upon receiving a pulse at the first potential, and outputs a second logic level upon receiving a pulse at the second potential. Output of these logic levels is maintained until the next pulse is received. The transmission line is preferably terminated at a potential intermediate between the first and second potentials.
摘要翻译：一种接口电路和方法，用于通过第一终端通过耦合到所述第一电子电路的传输线将第一电子电路的二进制逻辑信号传输到第二电子电路，并通过第二终端传输到所述第二电子电路。接口电路通过在二进制逻辑信号的每次下降转变时以第一电位发送脉冲并且在二进制逻辑信号的每个上升转变时以第二电位发送脉冲来发送二进制逻辑信号。在其他时候，驱动器电路的输出端子处于高阻抗状态。接收器电路在接收到处于第一电位的脉冲时输出第一逻辑电平，并且在接收到处于第二电位的脉冲时输出第二逻辑电平。这些逻辑电平的输出一直保持到接收到下一个脉冲。传输线优选终止于第一和第二电位之间的电位中间。

3. 发明授权

KR100315607B1 전위 발생 회로의 출력 전위가 목표 전위에 도달하는지의 여부를 검출하기 위한 전위 검출 회로 失效
标题翻译：用于检测潜在生成电路的输出潜在电位是否达到目标潜在或不可能的潜在检测电路
公开(公告)号：KR100315607B1
公开(公告)日：2001-12-12
申请号：KR1019990005321
申请日：1999-02-13
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 미하라마사아끼
IPC分类号： G01R19/00
CPC分类号： H03K5/153 , H03K5/2481 , H03K17/223 , H03K17/302
摘要： 플래시메모리에포함된전압발생회로(8.1)의출력단자 8.1a 및접지전위 GND 라인간에저항소자(22) 및 N 채널 MOS 트랜지스터(26)를직렬접속한다. MOS 트랜지스터(26)에일정한전류 I가흐르며, N 채널 MOS 트랜지스터(26)의드레인전위 VO1 및기준전위 Vr2를비교기(27)에의해비교한다. 전압변환효율△VO1/△VP1이 1로되어, 종래보다도전압검출정도가향상된다.

4. 发明公开

KR1020170125916A 저전압 임계의 정확한 검출 审中-实审
标题翻译：准确检测低电压阈值
公开(公告)号：KR1020170125916A
公开(公告)日：2017-11-15
申请号：KR1020177027702
申请日：2016-03-04
申请人： 리니어 테크놀러지 엘엘씨
发明人： 가드너,앤드류,조셉 , 드웰리,데이비드,매클레인
IPC分类号： G01R19/165 , H03K5/153 , G01R19/00 , H03K5/24
CPC分类号： H03K5/153 , G01R19/0092 , G01R19/16519 , G01R19/16538 , G01R19/16552 , G01R19/16571 , H03K5/24
摘要： 임계검출회로는전원과부하사이의전류가전류임계레벨에도달하는때를감지할수 있다. 임계검출회로는, 부하와직렬로연결된트랜지스터; 트랜지스터가전원과부하사이에전류를전도하고있는동안, 트랜지스터에걸친전압강하가일정하게하는피드백회로; 부하로정전류를전달하는정전류원; 및트랜지스터에걸친전압강하가전압임계레벨아래로떨어질때를나타내는비교기를포함한다.
摘要翻译：临界检测电路可以感测电源过载之间的电流何时达到电流阈值水平。阈值检测电路包括：与负载串联耦合的晶体管; 一个反馈电路，用于在晶体管在电源过载之间传导电流时使晶体管两端的电压降保持不变; 用于向负载提供恒定电流的恒流源; 还有一个比较器，用于指示晶体管两端的压降何时降到电压阈值以下。

5. 发明公开

KR1020140090736A 내부 스큐를 보상하는 반도체 장치 및 그것의 동작 방법 审中-实审
标题翻译：用于内部钻孔的半导体器件补偿及其操作方法
公开(公告)号：KR1020140090736A
公开(公告)日：2014-07-18
申请号：KR1020130002533
申请日：2013-01-09
申请人： 삼성전자주식회사
发明人： 송호빈 , 김태평 , 이천오
IPC分类号： H03K5/13 , H03L7/00
CPC分类号： H03K5/153
摘要： The present invention relates to a semiconductor device compensating an external device and internal skew without a training process. The semiconductor device according to the present invention comprises a signal generating part generating and outputting a reference signal; a first receiving part receiving the reference signal and outputting a first output signal; a second receiving part receiving the reference signal to output a second output signal; a delay part delaying the first output signal for a certain time and outputting a delay signal; a sample part sampling the second output signal based on the delay signal to output sampling data; and a skew controlling part controlling the delay part based on the sampling data.
摘要翻译：本发明涉及补偿外部设备的半导体器件和内部偏斜，而不需要训练过程。根据本发明的半导体器件包括产生并输出参考信号的信号产生部件; 接收参考信号并输出第一输出信号的第一接收部分; 接收所述参考信号以输出第二输出信号的第二接收部分; 延迟部分将所述第一输出信号延迟一定时间并输出延迟信号; 基于所述延迟信号对所述第二输出信号进行采样以输出采样数据的采样部分; 以及基于采样数据控制延迟部分的偏斜控制部分。

6. 发明授权

KR101298179B1 가우시안 펄스 형태를 가지는 초광대역의 디지털 펄스 발생기 有权
标题翻译：超高频数字脉冲发生器与高斯脉冲形状
公开(公告)号：KR101298179B1
公开(公告)日：2013-08-20
申请号：KR1020120032856
申请日：2012-03-30
申请人： 실리콘알엔디(주)
发明人： 유현진 , 어윤성
IPC分类号： H03K3/03 , H03K5/13
CPC分类号： H03K5/06 , H03K3/0315 , H03K5/153 , H03K2005/00202
摘要： PURPOSE: A digital pulse generator of ultrawide band having a Gaussian pulse shape is provided to generate impulse in all ultrawide frequency bands and change the bandwidth into an arbitrary signal. CONSTITUTION: A digital pulse generator comprises a time delay circuit (10), a latch circuit (20), a pulse sensing circuit (30), and a Gaussian envelope shaper (40). The time delay circuit generates multiple time delay pulses having a constant time delay by receiving a first clock pulse. The latch circuit receives the multiple time delay pulses from the time delay circuit and outputs the multiple time delay pulses by a second clock pulse, and controls each of outputs of the multiple time delay pulses by clear control signal. The pulse sensing circuit receives the multiple time delay pulses from the latch circuit, and outputs a pulse signal corresponding to a difference between signals delayed in the time delay circuit. The Gaussian envelope shaper outputs an impulse signal having a Gaussian shape by synthesizing the pulse signals output from the pulse sensing circuit. [Reference numerals] (AA) Time delay circuit
摘要翻译：目的：提供具有高斯脉冲形状的超宽带数字脉冲发生器，以在所有超宽频带中产生脉冲，并将带宽改变为任意信号。构成：数字脉冲发生器包括时间延迟电路（10），锁存电路（20），脉冲感测电路（30）和高斯包络整形器（40）。时间延迟电路通过接收第一时钟脉冲来产生具有恒定时间延迟的多个时间延迟脉冲。锁存电路从时间延迟电路接收多个时间延迟脉冲，并通过第二时钟脉冲输出多个时间延迟脉冲，并通过清除控制信号控制多个时间延迟脉冲的每个输出。脉冲检测电路从锁存电路接收多个时间延迟脉冲，并输出与时延电路中延迟的信号的差相对应的脉冲信号。高斯包络整形器通过合成从脉冲感测电路输出的脉冲信号输出具有高斯形状的脉冲信号。（附图标记）（AA）延时电路

7. 发明公开

KR1020070120145A 적응성 트립 포인트 검출을 위한 장치 및 방법들 无效
标题翻译：用于自适应三点检测的装置和方法
公开(公告)号：KR1020070120145A
公开(公告)日：2007-12-21
申请号：KR1020077023417
申请日：2006-03-31
申请人： 쌘디스크 3디 엘엘씨
发明人： 토르프,타일러 , 존슨,마크 , 하우크네스,브렌트
IPC分类号： H03K17/22 , H03K17/00
CPC分类号： H03K5/153 , H03K17/145 , H03K17/223
摘要： Apparatus and methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature, without requiring an externally-supplied reference signal.
摘要翻译：描述了用于提供自适应跳变点检测器电路的装置和方法，所述自适应跳变点检测器电路在输入信号节点处接收输入信号，并在输出信号节点处产生输出信号，输出信号在第一值变化到第二值时，超过跳点参考值。特别地，调整跳变点参考值以补偿过程或温度的变化，而不需要外部提供的参考信号。

8. 发明公开

KR1020040014153A 반도체 집적 회로 无效
标题翻译：半导体集成电路
公开(公告)号：KR1020040014153A
公开(公告)日：2004-02-14
申请号：KR1020030019030
申请日：2003-03-27
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 마츠모토야스히로 , 다나카고우지
IPC分类号： G11C5/14
CPC分类号： H03K5/19 , G06F1/26 , H03K5/153
摘要： PURPOSE: To provide a semiconductor integrated circuit capable of surely detecting oscillation generated due to the supply of excessive currents in an internal step-down power source circuit, and spontaneously suppressing oscillation by decreasing current supply capability at detecting oscillation. CONSTITUTION: In an oscillation detecting circuit 1, an internal voltage VDL is compared with an oscillation detection level where predetermined fluctuation is added to a reference voltage VREF, and when a voltage level higher than the oscillation detection level is confirmed the predetermined number of times in a fixed period, it is recognized that an oscillating state is set, and an H level oscillation detection signal ODE is outputted. At receiving the H level oscillation detection signal, a P channel MOS transistor 19 of an internal step-down power source circuit is turned off, and current supply from a drive transistor 17 to an internal power supply node 2 is stopped.
摘要翻译：目的：提供一种半导体集成电路，其能够可靠地检测由于在内部降压电源电路中产生过大电流而产生的振荡，并且通过降低检测振荡时的电流供应能力来自发抑制振荡。构成：在振荡检测电路1中，将内部电压VDL与对基准电压VREF加上规定的波动的振荡检测电平进行比较，当确定高于振荡检测电平的电压电平时，在固定周期中，认为设定振荡状态，并输出H电平振荡检测信号ODE。在接收到H电平振荡检测信号时，内部降压电源电路的P沟道MOS晶体管19截止，并且从驱动晶体管17到内部电源节点2的电流停止。

9. 发明授权

KR100328833B1 반도체 메모리의 센스앰프 제어신호 발생회로 有权
标题翻译： SENSE放大器控制信号生成半导体存储器的电路
公开(公告)号：KR100328833B1
公开(公告)日：2002-03-14
申请号：KR1019990037831
申请日：1999-09-07
申请人： 에스케이하이닉스 주식회사
发明人： 정영한
IPC分类号： G11C7/06
CPC分类号： H03K5/153 , H03K5/151
摘要： 본발명은반도체메모리의센스앰프제어신호발생회로에관한것으로, 특히정상동작시와리프레쉬동작시의신호경로를달리하여리프레쉬동작시에는오버드라이빙구간의펄스폭을줄임으로써리프레쉬전류를감소시킬수 있는반도체메모리의센스앰프제어신호발생회로에관한것이다. 이와같은본 발명은센스앰프인에이블신호를소정의제 1 지연시간만큼지연시켜출력하는제 1 지연부와; 상기제 1 지연부의출력신호를소정의제 2 지연시간만큼지연시켜출력하는제 2 지연부와; 리프레쉬제어신호에따라상기제 1 지연부또는제 2 지연부로부터인가되는지연신호에대하여정상동작과리프레쉬동작으로구분하여논리연산을수행하는논리부;로구성되어, 정상동작시와리프레쉬동작시의오버드라이빙구간이서로다르게설정되도록하는것을특징으로한다.

10. 发明授权

KR1019900006540B1 펄스발생회로 失效
标题翻译：脉冲发生电路
公开(公告)号：KR1019900006540B1
公开(公告)日：1990-09-07
申请号：KR1019840002811
申请日：1984-05-23
申请人： 가부시끼가이샤 도시바
发明人： 데즈까히데하루
IPC分类号： H03K3/00
CPC分类号： H03K5/153
摘要： The signal input at a terminal (15) is inverted by a resistor (r1) and transistor (Q1). Two switching transistors (Q9,Q6) are connected to a voltage rail (Vcc) through a load resistor (r4) and to an earth rail. A pair of transistors (Q3,Q7) provide a switch control circuit which charges the collector-base capacitance of another transistor (Q5) in response to the input signal going high level and discharges that capacitance in response to the input signal going low level. The first switching transistor (Q9) is set by the switch control circuit to turn on and off respectively in response to the capacitor voltage being above and below a predetermined voltage. The collector-base capacitance of further transistor (Q4) is charged by a second switch control circuit formed by transistors (Q2,Q5) in response to a high- level signal output from the inverting circuit (r1,Q1).
摘要翻译：在端子（15）处输入的信号由电阻（r1）和晶体管（Q1）反相。两个开关晶体管（Q9，Q6）通过负载电阻（r4）和地线连接到电压轨（Vcc）。一对晶体管（Q3，Q7）提供开关控制电路，其响应于输入信号变为高电平而对另一晶体管（Q5）的集电极基极电容进行充电，并且响应于输入信号为低电平而放电该电容。响应于电容器电压高于和低于预定电压，第一开关晶体管（Q9）由开关控制电路分别设置为导通和关断。响应于从反相电路（r1，Q1）输出的高电平信号，另一晶体管（Q4）的集电极基极电容由由晶体管（Q2，Q5）形成的第二开关控制电路充电。

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