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1. 发明公开

KR1020040107433A 저항체를 갖는 배선 기판 및 배선 기판의 제조 방법 无效
标题翻译：具有涂覆在电阻表面上的电阻和导体的电路板及其制造方法
公开(公告)号：KR1020040107433A
公开(公告)日：2004-12-20
申请号：KR1020040043286
申请日：2004-06-12
申请人： 신꼬오덴기 고교 가부시키가이샤
发明人： 다나카고이치
IPC分类号： H05K1/16
CPC分类号： H01C17/24 , H01C17/22 , H05K1/167 , H05K2201/0347 , H05K2201/035 , H05K2203/171
摘要： PURPOSE: A circuit board and a method for manufacturing the same are provided to achieve improved reliability by accurately adjusting electrical resistance value of resistor. CONSTITUTION: A method for manufacturing a circuit board comprises a first step of forming a circuit pattern on a surface of a circuit board(10); a second step of printing a resistor(16) between electrodes of the circuit pattern with a resistor paste; a third step of measuring electrical resistance value of the resistor; and a fourth step of forming a conductor(18) of a predetermined area, for adjusting electrical resistance value, wherein the conductor has a conductivity higher than the resistor, in case where the measured electrical resistance value does not fall within a tolerance of design.
摘要翻译：目的：提供一种电路板及其制造方法，通过精确调整电阻器的电阻值来提高可靠性。构成：制造电路板的方法包括在电路板（10）的表面上形成电路图案的第一步骤。在电路图形的电极之间用电阻浆料印刷电阻器（16）的第二步骤; 测量电阻器的电阻值的第三步骤; 以及形成预定面积的导体（18）的第四步骤，用于调节电阻值，其中当测量的电阻值不在设计的公差范围内时，导体的导电率高于电阻器。

2. 发明公开

KR20180049987A 칩 저항기 审中-公开
公开(公告)号：KR20180049987A
公开(公告)日：2018-05-14
申请号：KR20160146575
申请日：2016-11-04
IPC分类号： H01C17/065 , H01C1/14 , H01C17/00
CPC分类号： H01C17/006 , H01C1/01 , H01C1/028 , H01C1/14 , H01C17/22 , Y10T29/49082
摘要： 본발명의일 실시예에따른칩 저항기는, 기판과, 기판의일면상에배치된제1 및제2 전극과, 제1 전극과제2 전극을전기적으로연결하도록배치되고구리-망간-주석(Cu-Mn-Sn) 합금을포함하는저항체를포함하고, 구리-망간-주석(Cu-Mn-Sn) 합금에서망간(Mn)의비율은 11% 이상 20% 이하이고주석(Sn)의비율은 2% 이상 8% 이하이고망간-주석(Mn-Sn)의비율은 13.5% 이상 22.5% 이하일수 있다.

3. 发明授权

KR1019900006963B1 고정도 궤환 저항체와 출력증폭기를 구비한 저렴한 디지탈-아날로그 변환기 失效
标题翻译：具有高精度反馈电阻和输出放大器的廉价数模转换器
公开(公告)号：KR1019900006963B1
公开(公告)日：1990-09-25
申请号：KR1019860003713
申请日：1986-05-13
申请人： 버어-브라운코오퍼레이션
发明人： 지미레이네일러 , 데이비드에프미이터스 , 로버트엘화이트
IPC分类号： H03M1/66
CPC分类号： H01C17/22 , H03M1/089 , H03M1/785
摘要： Resistors defining bit streams are connected to the emitter of a source transistor and to a first supply voltage conductor. Devices connected to the current summing conductor define the magnitude of the current in the sum conductor. A trimmable integrated potentiometer is in the temp. compensation reference voltage device and has a coarse trimming region with a number of connection fingers and two fine trimming regions. A device couples the voltage from the potentiometer's tapping line to the bases of the bit stream source transistors.
摘要翻译：定义位流的电阻器连接到源晶体管的发射极和第一电源电压导体。连接到电流求和导体的器件定义总导体中电流的大小。可调整的集成电位器在温度补偿参考电压装置，具有多个连接指状物和两个细微修整区域的粗调整区域。一个器件将电位器的分接线的电压耦合到位流源晶体管的基极。

4. 发明公开

KR1020140000622A 칩 저항기를 제조하는 방법 有权
标题翻译：制造芯片电阻的方法
公开(公告)号：KR1020140000622A
公开(公告)日：2014-01-03
申请号：KR1020130036182
申请日：2013-04-03
申请人： 랄렉 일렉트로닉 코포레이션
发明人： 첸풀
IPC分类号： H01C17/06 , H01C7/00
CPC分类号： H01C17/006 , H01C7/00 , H01C17/22 , Y10T156/108
摘要： In a method of manufacturing a chip resistor (2), a semi-product (43) is formed by sandwiching an electric-insulating material layer (5) between an electric-conducting material layer (41) and a heat-dissipating material layer (42). Resistor sections (46) arranged in an array on the semi-product (43) are formed by forming longitudinal first slots (44) and transverse second slots (45) through the semi-product (43). Slits are formed on a first layer (411) of each resistor section to form a resistor main body (21). A dividing slot (231) is formed on a second layer (421) of each resistor section (46). Electrodes (24) are formed to be electrically connected to opposite ends (214) of the resistor main body (21). The resistor sections (46) are trimmed from the semi-product (43) to obtain the chip resistors (2). [Reference numerals] (S01) Form a semi-product; (S011) Coat a heat-conductive polymer material on one of an electric-conducting material layer and a heat-dissipating material layer; (S012) Stack the other one of the electric-conducting material layer and the heat-dissipating material layer on the heat-conductive polymer material; (S013) Heat the electric-conducting material layer and the heat-dissipating material layer under a vacuum condition; (S02) Form resistor sections arranged in an array on the semi-product; (S021) Form longitudinally extending first slots through the semi-product; (S022) Form longitudinally extending second slots through the semi-product; (S03) Form slits on a first layer of each resistor section to form a resistor main body; (S04) Form a slot on a second layer of each resistor section to form a heat dissipating layer; (S05) Form two electrodes electrically and respectively connected to opposite ends of the resistor main body; (S06) Trim the resistor sections from the semi-product to obtain chip resistors
摘要翻译：在制造片状电阻器（2）的方法中，通过将电绝缘材料层（5）夹在导电材料层（41）和散热材料层（41）之间而形成半成品（43） 42）。通过形成通过半成品（43）的纵向第一槽（44）和横向第二槽（45）而形成在半产品（43）上排列成阵列的电阻部分（46）。在每个电阻器部分的第一层（411）上形成狭缝以形成电阻器主体（21）。分隔槽（231）形成在每个电阻器部分（46）的第二层（421）上。电极（24）形成为电连接到电阻器主体（21）的相对端（214）。从半成品（43）修剪电阻器部分（46）以获得芯片电阻器（2）。（附图标记）（S01）形成半成品; （S011）在导电材料层和散热材料层之一上覆盖导热性高分子材料，（S012）将导电性材料层和散热材料层中的另一方堆叠在导热性聚合物材料上; （S013）在真空条件下加热导电材料层和散热材料层; （S02）在半成品上排列成阵列的形成电阻器部分; （S021）通过半成品纵向延伸第一槽; （S022）通过半成品纵向延伸第二槽; （S03）在每个电阻器部分的第一层上形成狭缝以形成电阻器主体; （S04）在每个电阻器部分的第二层上形成槽，以形成散热层; （S05）电连接并分别连接到电阻器主体的相对端的两个电极; （S06）从半产品中修剪电阻器部分，以获得芯片电阻

5. 发明公开

KR1020120127275A 볼티지 레귤레이터 有权
标题翻译：电压稳压器
公开(公告)号：KR1020120127275A
公开(公告)日：2012-11-21
申请号：KR1020120049671
申请日：2012-05-10
申请人： 에스아이아이 세미컨덕터 가부시키가이샤
发明人： 사카구치가오루 , 이무라다카시
IPC分类号： G05F1/573 , G05F1/565 , G05F3/24 , G05F1/567 , H02H7/20
CPC分类号： G05F1/573 , G05F1/565 , G05F1/567 , G05F3/24 , H01C17/22 , H02H7/205
摘要： PURPOSE: A voltage regulator is provided to reduce a chip area by not using a test circuit. CONSTITUTION: A reference voltage circuit(103) outputs a reference voltage. A differential amplification circuit(104) compares the reference voltage and a voltage based on an output voltage. The differential amplification circuit controls a gate voltage of an output transistor(105). An overcurrent protection circuit(107) limits a current of the output transistor by detecting an overcurrent on the output transistor. [Reference numerals] (107) Overcurrent protection circuit
摘要翻译：目的：提供电压调节器，通过不使用测试电路来减少芯片面积。构成：参考电压电路（103）输出参考电压。差分放大电路（104）基于输出电压比较参考电压和电压。差分放大电路控制输出晶体管（105）的栅极电压。过电流保护电路（107）通过检测输出晶体管上的过电流来限制输出晶体管的电流。（附图标记）（107）过电流保护电路

6. 发明公开

KR1020120045329A 반도체 장치 및 그 전압 트리밍 방법 无效
标题翻译：半导体装置和电压调节方法
公开(公告)号：KR1020120045329A
公开(公告)日：2012-05-09
申请号：KR1020100106804
申请日：2010-10-29
申请人： 에스케이하이닉스 주식회사
发明人： 임재혁
IPC分类号： G11C5/14 , G11C5/02
CPC分类号： G05F1/56 , H01C17/22 , Y10T307/305
摘要： PURPOSE: A semiconductor device and a voltage trimming method thereof are provided to implement an optimum operation property by independently trimming a reference voltage at each slave chip. CONSTITUTION: A master chip and a plurality of slave chips(SLAVE CHIP1 to SLAVE CHIP4) are vertically laminated. A semiconductor chip through line(101A) passes through the master chip and the plurality of slave chips to be electrically connected. The plurality of slave chips receive a reference voltage from the master chip through the semiconductor chip through line and generates an internal voltage through a trimming reference voltage after the reference voltage is independently trimmed.
摘要翻译：目的：提供半导体器件及其电压修整方法，通过在每个从芯片上独立地调整参考电压来实现最佳操作特性。构成：主芯片和多个从芯片（SLAVE CHIP1至SLAVE CHIP4）垂直层压。通过线路（101A）的半导体芯片通过主芯片和多个从芯片进行电连接。多个从芯片从主芯片通过半导体芯片通过线路接收参考电压，并且在参考电压被独立地修整之后通过修整参考电压产生内部电压。

7. 发明授权

KR1019950013898B1 반도체 장치의 제조 방법 失效
标题翻译：通过功能调整可以调整输出特性的半导体器件
公开(公告)号：KR1019950013898B1
公开(公告)日：1995-11-17
申请号：KR1019910005460
申请日：1991-04-04
申请人： 가부시끼가이샤 도시바
发明人： 오하따유 , 기따하라고이찌 , 다까기요수께
IPC分类号： H01L27/04
CPC分类号： H01C17/22 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： 내용 없음.

8. 发明授权

KR101528207B1 칩 저항기를 제조하는 방법 有权
标题翻译：制造芯片电阻的方法
公开(公告)号：KR101528207B1
公开(公告)日：2015-06-11
申请号：KR1020130036182
申请日：2013-04-03
申请人： 랄렉 일렉트로닉 코포레이션
发明人： 첸풀
IPC分类号： H01C17/06 , H01C7/00
CPC分类号： H01C17/006 , H01C7/00 , H01C17/22 , Y10T156/108
摘要： 칩저항기(2)를제조하는방법에서, 전기도전재료층(41)과열소산재료층(42) 사이에전기절연재료층(5)을개재함으로써반제품(43)이형성된다. 반제품(43) 상에어레이로배열된저항기섹션(46)은반제품(43)을관통하여길이방향의제1 슬롯(44) 및횡방향의제2 슬롯(45)을형성함으로써형성된다. 저항기주몸체(21)를형성하기위해각각의저항기섹션의제1 층(411) 상에슬릿(211)이형성된다. 각각의저항기섹션(46)의제2 층(421) 상에는분할슬롯(231)이형성된다. 저항기주몸체(21)의상호반대쪽말단부(214)에전기접속되도록전극(24)이형성된다. 반제품(43)으로부터저항기섹션(46)을트리밍하여칩 저항기(2)를획득한다.

9. 发明公开

KR1020120047925A 전자부품 및 그의 제조방법 无效
标题翻译：电子元件和相应的生产方法
公开(公告)号：KR1020120047925A
公开(公告)日：2012-05-14
申请号：KR1020127002667
申请日：2010-06-16
申请人： 이자벨렌휘테 호이슬러 게엠베하 운트 코. 카게
发明人： 헷츨러울리히
IPC分类号： H01C1/14 , H01C17/22 , H01C17/28 , G01R1/20 , H01M10/48 , G01R31/36 , H01L23/00
CPC分类号： H01M10/48 , G01R1/203 , G01R31/36 , H01C1/14 , H01C17/22 , H01C17/28 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2924/01087 , H01L2924/14 , H01L2924/1433 , H01L2924/19043 , H01L2924/3011 , Y10T29/49204 , H01L2924/00
摘要： 본 발명은 적어도 하나의 플레이트-형상부(2,3)와 플레이트-형상부에 전기적 접촉을 위한 적어도 하나의 접속부(7,8)을 포함하는 전자부품(1), 상세하게는 저-저항 전류-감응 저항기에 관한 것이다. 본 발명에 따르면, 전류 흐름에 의해 생성된 전압낙차를 측정하기 위한 접속부(7,8)는 플레이트-형상부(2,3)에 스탬핑 및 나선 형상화에 의해 형성된다.

10. 发明公开

KR1020110126417A 저항기 및 저항기 형성방법 无效
标题翻译：电阻和形成电阻的方法
公开(公告)号：KR1020110126417A
公开(公告)日：2011-11-23
申请号：KR1020100046083
申请日：2010-05-17
申请人： 삼성전기주식회사
发明人： 위홍복 , 소원욱 , 박종흠 , 박영귀
IPC分类号： H01C10/00
CPC分类号： H01C17/22 , Y10T29/49082
摘要： PURPOSE: A resistor and a method for forming a resistor are provided to reduce manufacturing costs for a resistor by forming most of penetration holes to control a resistance value with a general process. CONSTITUTION: A conductor, in which a plurality of penetration holes is formed, is provided(S110). The resistance value of a resistance area is measured(S120). The resistance value of the resistance area is corrected by eliminating selectively parts which connect a plurality of penetration holes(S130). A solder resist layer is laminated in the conductor(S140). A pair of electrodes is formed in the both sides of the resistance area(S150).
摘要翻译：目的：提供电阻器和形成电阻器的方法，以通过形成大部分穿透孔以通过一般工艺来控制电阻值来降低电阻器的制造成本。构成：提供形成有多个贯通孔的导体（S110）。测量电阻面积的电阻值（S120）。通过消除选择连接多个贯通孔的部件来修正电阻区域的电阻值（S130）。导电体层叠阻焊层（S140）。在电阻区域的两侧形成一对电极（S150）。

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