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1. 发明公开

KR1020140007346A 강유전체 커패시터를 사용한 아날로그 메모리 审中-实审
标题翻译：使用电磁电容器的模拟记忆
公开(公告)号：KR1020140007346A
公开(公告)日：2014-01-17
申请号：KR1020137016622
申请日：2011-11-17
申请人： 래디언트 테크놀러지즈, 인코포레이티드
发明人： 에반스,조셉,티. , 워드,칼빈,비.
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： 각각이 강유전체 커패시터를 포함하는 복수의 강유전체 메모리 셀을 구비한 강유전체 메모리가 개시된다. 강유전체 메모리는 독출 라인과 기입 라인 및 복수의 강유전체 메모리 셀 선택 버스를 포함하고, 하나의 선택 버스가 강유전체 메모리 셀들 각각에 대응한다. 강유전체 메모리 셀들 각각은 강유전체 메모리 셀에 대응하는 강유전체 메모리 셀 선택 버스 상의 신호들에 응답하여, 강유전체 메모리 셀을 독출 라인과 기입 라인에 각각 연결하기 위한 제1 및 제2 게이트를 포함한다. 기입 회로가 적어도 3가지 상태를 가진 데이터값에 의해 결정된 값을 가진 전하를 기입 라인에 현재 연결된 강유전체 메모리 셀의 강유전체 커패시터에 저장되게 한다. 독출 회로가 독출 라인에 현재 연결된 강유전체 메모리 셀의 강유전체 커패시터에 저장된 전하를 측정하여, 상태들 중 하나의 상태에 대응하는 출력값을 생성한다.

2. 发明授权

KR100835489B1 불휘발성 강유전체 메모리를 포함하는 ＲＦＩＤ에서의 클록발생 장치 失效
标题翻译：用于在非易失性电磁记忆体中产生时钟的装置
公开(公告)号：KR100835489B1
公开(公告)日：2008-06-04
申请号：KR1020070001048
申请日：2007-01-04
申请人： 에스케이하이닉스 주식회사
发明人： 강희복
IPC分类号： G11C11/22 , G11C16/32 , G11C16/30 , G11C5/14
CPC分类号： G06K19/0723 , G11C11/2293 , G11C11/2297 , H03K19/0016
摘要： A device for generating a clock in an RFID(Radio Frequency Identification) with a non-volatile ferroelectric memory is provided to reduce cost and to improve operation performance of an RFID tag by optimizing the configuration of a clock generation circuit. A clock oscillation voltage adjustment part(162) maintains a constant level of a first voltage according to a first valid resistor having positive slope characteristics and a second valid resistor having negative slope characteristics in correspondence to level variation of a power supply voltage. A clock oscillation part(164) adjusts an oscillation frequency of an internal clock according to the first voltage. A clock buffer voltage adjustment part(166) maintains a constant level of a second voltage according to a third valid resistor having positive slope characteristics and a fourth valid resistor having negative slope characteristics in correspondence to the level variation of the power supply voltage. A clock buffer part(168) generates an inverted internal clock with opposite phase to the internal clock by buffering the internal clock according to the second voltage.
摘要翻译：提供了一种利用非挥发性铁电存储器在RFID（射频识别）中产生时钟的装置，通过优化时钟发生电路的配置来降低成本并提高RFID标签的操作性能。时钟振荡电压调整部分（162）根据具有正斜率特性的第一有效电阻器和对应于电源电压的电平变化具有负斜率特性的第二有效电阻器维持第一电压的恒定电平。时钟振荡部分（164）根据第一电压调节内部时钟的振荡频率。时钟缓冲电压调整部分166根据具有正斜率特性的第三有效电阻器和对应于电源电压的电平变化的负斜率特性的第四有效电阻器维持恒定电平的第二电压。时钟缓冲器部分（168）通过根据第二电压缓冲内部时钟来产生与内部时钟相反的反相内部时钟。

3. 发明公开

KR1020080011025A 불휘발성 강유전체 메모리 장치 및 그 리프레쉬 방법 失效
标题翻译：非易失性电介质存储器件及其刷新方法
公开(公告)号：KR1020080011025A
公开(公告)日：2008-01-31
申请号：KR1020060132602
申请日：2006-12-22
申请人： 에스케이하이닉스 주식회사
发明人： 강희복
IPC分类号： G11C11/22 , G11C11/401 , G11C11/406
CPC分类号： G11C11/225 , G11C5/025 , G11C11/2253 , G11C11/2293 , H01L27/11502
摘要： A non-volatile ferroelectric memory device and a refresh method thereof are provided to improve data retention characteristics by recovering degraded cell data by performing refresh in a specific period as maintaining original data when a power is turned off. A ferroelectric memory device includes a nonvolatile memory cell performing data read/write operation, and includes a register and a refresh control unit(110). The register stores information of the memory cell. The refresh control unit performs refresh operation in a specific refresh period by using the information stored in the register in order to improve retention characteristics of data stored in the memory cell.
摘要翻译：提供了一种非挥发性铁电存储器件及其刷新方法，以通过在特定时段内进行刷新来恢复劣化的单元数据，从而通过在电源关闭时保持原始数据来提高数据保持特性。铁电存储器件包括执行数据读/写操作的非易失性存储单元，并且包括寄存器和刷新控制单元（110）。寄存器存储存储单元的信息。刷新控制单元通过使用存储在寄存器中的信息在特定刷新周期中执行刷新操作，以便改善存储在存储单元中的数据的保持特性。

4. 发明公开

KR1020070104825A 불휘발성 강유전체 메모리를 포함하는 ＲＦＩＤ에서의파워-온 리셋 회로 失效
标题翻译： RFID中的上电复位电路与非易失性存储器
公开(公告)号：KR1020070104825A
公开(公告)日：2007-10-29
申请号：KR1020070007436
申请日：2007-01-24
申请人： 에스케이하이닉스 주식회사
发明人： 강희복
IPC分类号： G11C11/22 , G11C16/30 , G11C16/20
CPC分类号： G06K19/0723 , G11C11/2293 , G11C11/2297 , H03K19/0016
摘要： A power-on reset circuit in an RFID(Radio Frequency IDentification) with a non-volatile ferroelectric memory is provided to generate a reset signal stably regardless of power-up slope by having delay time for system stabilization after a power-on reset sensing voltage arrives in the power-on reset circuit of the RFID. A pull-up current source(151) supplies a pull-up current. A ferroelectric capacitor part is connected between the pull-up current source and a ground voltage stage. A driver outputs a reset signal by being connected to a connection node of the pull-up current source and the ferroelectric capacitor part. A pull-up device supplies a pull-up voltage to the driver according to the output of one end of the driver. The ferroelectric capacitor part includes a plurality of ferroelectric capacitors connected between the pull-up current source and the ground voltage stage in parallel.
摘要翻译：提供具有非挥发性铁电存储器的RFID（射频识别）中的上电复位电路，通过在上电复位感测电压之后具有用于系统稳定的延迟时间，稳定地产生复位信号，而不管上电斜率如何到达RFID的上电复位电路。上拉电流源（151）提供上拉电流。铁电电容器部分连接在上拉电流源和地电压级之间。驱动器通过连接到上拉电流源和铁电电容器部分的连接节点来输出复位信号。上拉装置根据驱动器一端的输出向驱动器提供上拉电压。铁电电容器部分包括并联连接在上拉电流源和地电压级之间的多个铁电电容器。

5. 发明公开

KR20180072239A 반도체 메모리 장치의 데이터 정렬 회로, 반도체 메모리 장치 및 반도체 메모리 장치의 데이터 정렬 방법 审中-公开
公开(公告)号：KR20180072239A
公开(公告)日：2018-06-29
申请号：KR20160175583
申请日：2016-12-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： JEON SEONG HWAN , HA KYUNG SOO , HEO JIN SEOK , SONG IN DAL , CHOI JUNG HWAN
IPC分类号： G11C7/10 , G11C11/4093
CPC分类号： G11C11/4023 , G11C7/222 , G11C11/2293
摘要： 반도체메모리장치의데이터정렬회로는데이터샘플링회로, 분주회로, 선택신호생성기및 데이터정렬블록을포함한다. 상기데이터샘플링회로는메모리컨트롤러로부터직렬입력되는데이터를데이터스트로브신호에기초하여샘플링하여데이터시퀀스로제공한다. 상기분주회로는상기메모리컨트롤러로부터제공되는클럭신호를분주하고, 분주된클럭신호를상기데이터스트로브신호에기초하여샘플링하여정렬제어신호를생성한다. 상기선택신호생성기는상기데이터스트로브신호의에지와상기정렬제어신호의논리레벨에기초하여선택신호를제공한다. 상기데이터정렬블록은상기선택신호에응답하고, 상기정렬제어신호에기초하여상기데이터시퀀스를병렬로정렬하여내부데이터를생성한다. 상기클럭신호는상기반도체메모리장치에서상기메모리컨트롤러로부터의커맨드를샘플링하는데사용한다.

6. 发明公开

KR1020040083250A 타이밍 레퍼런스 제어 기능을 갖는 불휘발성 강유전체메모리 장치 및 그 제어 방법 失效
标题翻译：具有时序参考控制功能的非易失性存储器件及其控制方法
公开(公告)号：KR1020040083250A
公开(公告)日：2004-10-01
申请号：KR1020030017836
申请日：2003-03-21
申请人： 에스케이하이닉스 주식회사
发明人： 강희복
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C11/2275 , G11C11/2293
摘要： PURPOSE: A nonvolatile ferroelectric memory device having a timing reference control function and its control method are provided to improve a data access time by improving a structure of a bus to read and write data and by storing data read and written by a register. CONSTITUTION: A plurality of cell array blocks(500) comprise a nonvolatile ferroelectric memory respectively, and amplify a sensing voltage of cell data in a reference timing strobe period by referring to a time axis. A read/write data register array part(300) stores read data applied from the plurality of cell array blocks while a read lock control signal is enabled, and it stores the read data or input data written to the plurality of cell array blocks while a write lock control signal is enabled. A read data bus part(400) is connected to the plurality of cell array blocks in common, and outputs the read data to the read/write data register array part. And a write data bus part(600) is connected to the plurality of cell array blocks in common and outputs the read data or the input data to the plurality of cell array blocks.
摘要翻译：目的：提供具有定时参考控制功能的非易失性铁电存储器件及其控制方法，通过改善总线读取和写入数据的结构以及通过存储由寄存器读取和写入的数据来改善数据存取时间。构成：多个单元阵列块（500）分别包括非易失性铁电存储器，并且通过参考时间轴在参考定时选通周期中放大单元数据的感测电压。读/写数据寄存器阵列部分（300）存储从读取锁定控制信号使能时从多个单元阵列块施加的读取数据，并且存储写入多个单元阵列块的读取数据或输入数据，而写锁定控制信号被使能。读数据总线部分（400）共同连接到多个单元阵列块，并将读出的数据输出到读/写数据寄存器阵列部分。并且写入数据总线部分（600）共同连接到多个单元阵列块，并将读取的数据或输入数据输出到多个单元阵列块。

7. 发明授权

KR100924204B1 ＲＦＩＤ 장치 失效
标题翻译：无线电频率识别装置
公开(公告)号：KR100924204B1
公开(公告)日：2009-10-29
申请号：KR1020080053719
申请日：2008-06-09
申请人： 에스케이하이닉스 주식회사
发明人： 강희복
IPC分类号： G11C11/22 , G06K19/077
CPC分类号： G06K19/0723 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2293
摘要： PURPOSE: An RFID device is provided to immediately restore a stored flag data although temporary interruption of a power source is generated during an operation of an RFID tag. CONSTITUTION: An RFID device includes an analog block, a digital block, and a memory block. The memory block reads/writes data to a cell array part including a nonvolatile ferroelectric capacitor device. The analog block includes a short-term memory(180) in activating a short-term data light signal. The short-term memory temporarily stores a short-term data for a predetermined data retention time. The short-term data is applied from the digital block, and includes information about a flag data. The analog block provides the short-term data stored to the short-term memory to the digital block. The short-term memory stores the short-term data for a data retention time regardless of an on/off state of the power source.
摘要翻译：目的：提供RFID设备以便立即恢复存储的标志数据，尽管在RFID标签的操作期间产生电源的暂时中断。构成：RFID设备包括模拟块，数字块和存储块。存储块读/写数据到包括非易失性铁电电容器件的单元阵列部分。模拟块包括短路存储器（180），用于激活短期数据光信号。短期存储器暂时存储用于预定数据保留时间的短期数据。从数字块应用短期数据，并且包括关于标志数据的信息。模拟模块将存储在短期存储器中的短期数据提供给数字模块。短期存储器存储用于数据保持时间的短期数据，而不管电源的开/关状态如何。

8. 发明公开

KR1020020082995A 강유전체 메모리 장치에서의 기준전압 발생 장치 失效
标题翻译：电力存储器件中的参考电压发生器
公开(公告)号：KR1020020082995A
公开(公告)日：2002-11-01
申请号：KR1020010022227
申请日：2001-04-25
申请人： 에스케이하이닉스 주식회사
发明人： 계훈우
IPC分类号： G11C11/22
CPC分类号： G11C11/2297 , G11C5/147 , G11C11/221 , G11C11/2293
摘要： PURPOSE: A reference voltage generator in a ferroelectric memory device is provided, which can increase an operation lifetime of the device due to relaxation and fatigue phenomenon. CONSTITUTION: A number of reference cells(60) comprises the first switching transistor(N601) whose gate is connected to a reference word line(RWL) and one side is connected to a bit line(bit1), and a ferroelectric capacitor(C60) whose one side is connected to the first switching transistor and another side is connected to a reference plate line(RPL), and the second switching transistor(N602) whose gate is connected to a restore word line(REST_WL) and one side is connected to another side of the first switching transistor and restores the ferroelectric capacitor by being connected in common with one side of the ferroelectric capacitor. A delay chain(62) outputs a delayed value to maintain a restored pulse width by inputting the reference plate line. And a logic part(61) outputs a 'logic high' to another side of the second switching transistor by receiving an output of the delay chain and the reference plate line.
摘要翻译：目的：提供铁电存储器件中的参考电压发生器，由于松弛和疲劳现象，可增加器件的使用寿命。构成：多个参考单元（60）包括其栅极连接到基准字线（RWL）并且一侧连接到位线（bit1）的第一开关晶体管（N601）和铁电电容器（C60）其一侧连接到第一开关晶体管，另一侧连接到参考板线（RPL），并且其门连接到恢复字线（REST_WL）并且一侧的第二开关晶体管（N602）连接到第一开关晶体管的另一侧，通过与铁电电容器的一侧共同连接来恢复铁电电容器。延迟链（62）通过输入参考板线输出延迟值以维持恢复的脉冲宽度。并且逻辑部分（61）通过接收延迟链和参考板线的输出而向第二开关晶体管的另一侧输出“逻辑高”。

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