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1. 发明授权

KR101734718B1 전동식 파워 스티어링용 모터의 외란 보상 시스템 有权
标题翻译：电动助力转向用电动机的干扰补偿系统
公开(公告)号：KR101734718B1
公开(公告)日：2017-05-11
申请号：KR1020150177858
申请日：2015-12-14
申请人： 현대자동차주식회사 , 한국과학기술원
发明人： 한민우 , 성우제 , 이종호 , 김성준 , 김경수 , 김용훈
IPC分类号： H02P21/00
CPC分类号： B62D5/046 , H02P6/08 , H02P6/28 , H02P23/0004
摘要： 본발명은전동식파워스티어링용모터의외란보상시스템에관한것으로서, 더욱상세하게는폐루프기반의입력값예측모델부를기반으로외란보상이이루어지도록한 전동식파워스티어링용모터의외란보상시스템에관한것이다. 즉, 본발명은폐루프기반의입력값예측모델부에서지령(전류지령값)으로부터입력값(모터에입력되는전압값)을별도로예측하고, 이예측된입력값이피드백제어부에서에러보상된입력값과차이가존재하는경우, 원하는외란주파수대역에맞는외란보상이이루어지도록한 전동식파워스티어링용모터의외란보상시스템을제공하고자한 것이다.
摘要翻译：本发明涉及电机，用于电动动力转向的干扰补偿系统，并且更具体地，涉及基于用于电机驱动的一个所述输入值的预测模型，以使干扰补偿由基于动力转向电动机部件的闭环的干扰补偿系统。即，从命令（电流指令值）在本发明中的输入，节隐蔽输入到由（电压值输入到电动机）分开，并且该示例中，输入值的侧预测的基于循环的预测模型值是在反馈控制输入误差补偿本发明提供一种用于电动助力转向的电动机的扰动补偿系统，其中根据期望的扰动频带执行扰动补偿。

2. 发明公开

KR1020120020614A 수크로오즈와 글리세롤을 동시에 이용하는 신규 숙신산 생성 변이 미생물 및 이를 이용한 숙신산 제조방법 有权
标题翻译：通过在同一时间使用二倍体蔗糖和甘油来生产具有高效果的酸性农药的新型工程化微生物和使用该方法制备磺酸的方法
公开(公告)号：KR1020120020614A
公开(公告)日：2012-03-08
申请号：KR1020100084327
申请日：2010-08-30
申请人： 한국과학기술원
发明人： 이상엽 , 이정욱 , 최솔 , 이종호
IPC分类号： C12N1/21 , C12N15/52 , C12P7/40
CPC分类号： C12P7/46 , C12N1/20 , C12N15/52 , C12R1/01
摘要： PURPOSE: A mutant microorganism which produces succinic acid is provided to maximize fermentation yield and to minimize by-products. CONSTITUTION: A mutant microorganism uses sucrose and glycerol to produce succinic acid by weakening catabolic product suppressing metabolism of glycerol. The microorganism is lumen bacteria. The lumen bacteria are Mannheimia sp., Actinobacillus sp., or Anaerobiospirillum sp. Mannheimia sp. is Mannheimia succiniciproducens PALK(KCTC10973BP). A method for preparing succinic acid comprises: a step of culturing the mutant microorganism under anaerobic condition; and a step of collecting succinic acid from the culture liquid.
摘要翻译：目的：提供产生琥珀酸的突变微生物，以最大限度地发酵产量并使副产物最小化。构成：突变体微生物通过削弱分解代谢产物抑制甘油代谢，使用蔗糖和甘油来生产琥珀酸。微生物是管腔细菌。管腔细菌是Mannheimia sp。，放线杆菌属（Actinobacillus sp。）或Anaerobiospirillum sp。曼海星属是Mannheimia succiniciproducens PALK（KCTC10973BP）。制备琥珀酸的方法包括：在厌氧条件下培养所述突变体微生物的步骤; 以及从培养液中收集琥珀酸的步骤。

3. 发明公开

KR1020100022202A 다중안테나 시스템에서 송ㆍ수신 장치 및 방법 有权
标题翻译：多天线系统中发射和恢复的装置和方法
公开(公告)号：KR1020100022202A
公开(公告)日：2010-03-02
申请号：KR1020080080753
申请日：2008-08-19
申请人： 삼성전자주식회사 , 한국과학기술원
发明人： 이주현 , 이종호 , 황성수 , 강준혁 , 송원택 , 박경호 , 장남석
IPC分类号： H04B7/04 , H04L1/06
CPC分类号： H04B7/0639 , H04L25/0204 , H04L25/0228
摘要： PURPOSE: A transceiving method in a multiple antenna system for reducing necessary computational complexity in selection or the quantization of a coding word is provided to remove interference between multi users by quantizing error. CONSTITUTION: A transmitter receives a codebook index from a plurality of terminals(300). The transmitter selects the k terminal of a plurality of terminals(302). The transmitter generates the precoder matrices P put through to the codebook index of the selected terminal(304). The transmitter performs precoding(306). The transmitter transmits the transmission signal of which the precoding is performed for the first time slot(308).
摘要翻译：目的：提供一种多天线系统中的收发方法，用于减少编码字的选择或量化中必要的计算复杂度，以通过量化误差来消除多用户之间的干扰。构成：发射机从多个终端（300）接收码本索引。发射机选择多个终端的k个终端（302）。发射机产生预选码矩阵P放入所选终端的码本索引（304）。发射机执行预编码（306）。发射机发送对其进行第一时隙（308）的预编码的发送信号。

4. 发明公开

KR1020030065631A 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법 有权
标题翻译：双栅极FinFET器件及其制造方法
公开(公告)号：KR1020030065631A
公开(公告)日：2003-08-09
申请号：KR1020020005325
申请日：2002-01-30
申请人： 한국과학기술원
发明人： 이종호
IPC分类号： H01L27/092 , B82Y40/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： PURPOSE: A dual gate FinFET device and a fabricating method thereof are provided to reduce fabricating cost and parasitic resistance by using a bulk wafer and forming an epitaxial layer on a source/drain. CONSTITUTION: A dual gate FinFET device includes a bulk silicon substrate(2b), a Fin active region(4), the second oxide layer(10), a gate oxide layer, the first oxide layer(6), a gate(16), a source/drain, a contact region, and a metal layer. The Fin active region is formed on the center portion of an upper portion of the bulk silicon substrate. The second oxide layer is formed on the surface of the bulk silicon substrate. The gate oxide layer is formed at both sidewalls of the Fin region of the second oxide layer. The first oxide layer is formed on an upper surface of the Fin active region. The gate is formed on the first and the second oxide layers. The source/drain is formed at both sides of the Fin active region except for an overlapped part between the gate and the Fin active region. The contact region and the metal layer are formed on the contact part of the source, the drain, and the gate.
摘要翻译：目的：提供双栅极FinFET器件及其制造方法，以通过使用体晶片并在源极/漏极上形成外延层来降低制造成本和寄生电阻。构造：双栅极FinFET器件包括体硅衬底（2b），鳍状活性区域（4），第二氧化物层（10），栅极氧化物层，第一氧化物层（6），栅极（16）源极/漏极，接触区域和金属层。翅片有源区形成在体硅衬底的上部的中心部分上。第二氧化物层形成在体硅衬底的表面上。栅极氧化物层形成在第二氧化物层的鳍区域的两个侧壁处。第一氧化物层形成在Fin活性区的上表面上。栅极形成在第一和第二氧化物层上。源极/漏极形成在Fin有源区域的两侧，除了栅极和Fin有源区域之间的重叠部分之外。接触区域和金属层形成在源极，漏极和栅极的接触部分上。

5. 发明公开

KR1020020018774A 극소채널 ＭＯＳ 트랜지스터 제조방법 失效
标题翻译：用于制造具有超小通道的金属氧化物半导体晶体管的方法
公开(公告)号：KR1020020018774A
公开(公告)日：2002-03-09
申请号：KR1020000052039
申请日：2000-09-04
申请人： 한국과학기술원
发明人： 신형철 , 이종호 , 한상연 , 장성일
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/41775 , H01L29/41783 , H01L29/665 , H01L29/66643 , H01L29/78 , H01L29/7831
摘要： PURPOSE: A method for fabricating a metal-oxide-semiconductor(MOS) transistor having an ultra-small channel is provided to reduce a short channel effect, by electrically making an inversion layer connected to a source/drain by a conductive layer pattern so that the inversion layer plays the role of the source/drain. CONSTITUTION: A gate pattern where a gate insulation layer, a main gate and a capping layer are sequentially stacked is formed on a p-type semiconductor substrate(110). A separating insulation layer is formed on the entire surface of the resultant structure having the gate pattern. A material layer for a side surface gate which has a work function lower than that of the p-type semiconductor substrate and the main gate is formed on the separating insulation layer. The material layer for the side surface gate and the separating insulation layer are anisotropically etched to expose the semiconductor substrate and the capping layer and to form a separating insulation layer pattern and the side surface gate. An n-type source/drain(190b) is formed. The conductive layer pattern which connects the side surface gate adjacent to the source and/or the drain with the side surface gate adjacent to the drain, is formed on the resultant structure.
摘要翻译：目的：提供一种制造具有超小通道的金属氧化物半导体（MOS）晶体管的方法，以通过用导电层图案电连接到源极/漏极的反型层来减小短沟道效应，使得反演层起着源/漏的作用。构成：在p型半导体衬底（110）上形成栅极绝缘层，主栅极和覆盖层依次层叠的栅极图案。在具有栅极图案的合成结构的整个表面上形成分离绝缘层。在分离绝缘层上形成具有低于p型半导体衬底和主栅极的功函数的侧表面栅极的材料层。各向异性蚀刻用于侧表面栅极和分离绝缘层的材料层以暴露半导体衬底和覆盖层，并形成分离绝缘层图案和侧表面栅极。形成n型源极/漏极（190b）。将与源极和/或漏极相邻的侧表面栅极与邻近漏极的侧表面栅极连接的导电层图案形成在所得结构上。

6. 发明授权

KR100264396B1 측면형 전계방출소자의 제조방법 失效
标题翻译：用于制造后场发射装置的方法
公开(公告)号：KR100264396B1
公开(公告)日：2000-08-16
申请号：KR1019980010830
申请日：1998-03-27
申请人： 한국과학기술원
发明人： 신형철 , 양선아 , 이종호
IPC分类号： H01J1/30
摘要： PURPOSE: A method for manufacturing a lateral field emission display device is provided to form a cathode pattern, an anode pattern, and a gate pattern as one mask by using an electron beam lithography process. CONSTITUTION: A conductive layer is formed on a substrate including an insulating layer. The conductive layer is formed as the first conductive layer pattern, the second conductive layer pattern, and the third conductive layer pattern by performing a lithography process. The first conductive layer pattern forms a cathode electrode(11). The second conductive layer pattern forms an anode electrode(12). The third conductive layer pattern forms a gate electrode(13,13').
摘要翻译：目的：提供一种用于制造横向场发射显示装置的方法，以通过使用电子束光刻工艺形成阴极图案，阳极图案和作为一个掩模的栅极图案。构成：在包括绝缘层的基板上形成导电层。通过进行光刻工艺，导电层形成为第一导电层图案，第二导电层图案和第三导电层图案。第一导电层图案形成阴极电极（11）。第二导电层图案形成阳极电极（12）。第三导电层图案形成栅电极（13,13'）。

7. 发明公开

KR1019990076137A 측면형 전계방출소자의 제조방법 失效
标题翻译：用于制造侧面型场发射器件的方法
公开(公告)号：KR1019990076137A
公开(公告)日：1999-10-15
申请号：KR1019980010830
申请日：1998-03-27
申请人： 한국과학기술원
发明人： 신형철 , 양선아 , 이종호
IPC分类号： H01J1/30
摘要： 본 발명은 전자선 리소그래피를 이용하여 한 장의 마스크로 캐소드, 에노드, 게이트 전극을 형성시킬 수 있어, 제조공정을 단순화시킨 측면형 전계방출소자의 제조방법을 제공하는데 그 목적이 있다.
본 발명에 따르면, 전계방출소자의 제조방법에 있어서, 그 표면에 절연막이 형성된 기판상에 전도막을 형성하는 단계와; 전자선 리소그래피 공정을 통해 상기 전도막을 캐소드 전극 형성을 위한 제1전도막 패턴과, 에노드 전극 형성을 위한 제2전도막 패턴 및, 게이트 전극 형성을 위한 제3전도막 패턴으로 형성하는 단계 및: 상기 캐소드, 에노드, 게이트 전극의 팁을 미세 간격으로 형성하기 위해 상기 형성된 패턴에 열 산화를 수행하는 단계를 포함하며, 상기 제1전도막 내지 제3전도막의 패턴 형상은, 상기 캐소드 전극의 제1전도막과 상기 에노드 전극의 제2전도막이 상호 대향되고, 상기 게이트 전극의 제3전도막은 상호 대향되게 한 쌍을 구비하되, 상기 제1전도막과 상기 제2전도막의 접점은 상기 후속 단계를 통해 임의의 수 나노 스케일의 간격이 형성될 수 있도록 미세 구조로 형성하고, 상기 한 쌍의 제3전도막은 가능한 한 상기 제1전도막과 제2전도막의 접점에 가깝도 록 형성하는 것을 특징으로 하는 전계방출소자의 제조방법이 제공된다.

8. 发明公开

KR1020080109988A 다중안테나 시스템에서 격자축소 기반의 프리코딩 방법 및장치 无效
标题翻译：用于在多个天线中预测基于衰减的方法和装置
公开(公告)号：KR1020080109988A
公开(公告)日：2008-12-18
申请号：KR1020070058180
申请日：2007-06-14
申请人： 삼성전자주식회사 , 한국과학기술원
发明人： 이종호 , 윤상보 , 권영훈 , 황성수 , 정성윤 , 박현철 , 강준혁 , 김남식 , 허수영
IPC分类号： H04L25/49 , H04B7/02
CPC分类号： H04L25/49 , H04B7/0456 , H04L2025/03458
摘要： A method for precoding based lattice reduction using list quantizer in multiple antenna system and apparatus thereof are provided to obtain maximum performance like function of a sphere coder algorithm of low-complexity by analyzing quantum error pattern. A method for precoding based lattice reduction using list quantizer in multiple antenna system comprises the following steps: a step for inputting a symbol stream data for transmitting to a plurality of terminals; a step for coping an inputted symbol data as one or more identical stream data; a step for generating transmission signals mapped to a quantized signal made by a quantizing error pattern from an identical symbol stream data; and a step for selecting the smallest power value from among transmission signals.
摘要翻译：提供了一种使用多天线系统中的列表量化器进行基于预编码的格点退化的方法及其装置，以通过分析量子误差模式来获得诸如低复杂度的球体编码器算法的最大性能。一种使用多天线系统中的列表量化器进行基于预编码的晶格简化的方法包括以下步骤：输入用于发送到多个终端的符号流数据的步骤; 将输入的符号数据作为一个或多个相同的流数据进行处理的步骤; 用于从相同的符号流数据生成映射到由量化误差模式产生的量化信号的传输信号的步骤; 以及从发送信号中选择最小功率值的步骤。

9. 发明授权

KR100431489B1 플래쉬 메모리 소자 및 제조방법 有权
标题翻译： 플래쉬메모리소자및제조방법
公开(公告)号：KR100431489B1
公开(公告)日：2004-05-12
申请号：KR1020010054055
申请日：2001-09-04
申请人： 한국과학기술원
发明人： 이종호 , 신형철
IPC分类号： H01L21/8247 , B82Y10/00
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/785 , H01L29/7854 , H01L29/7881 , H01L29/792
摘要： The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element. A flash memory element comprises: a first oxide film formed on a surface of a silicon substrate; a fin active area vertically formed on the first oxide film; a gate tunneling oxide film formed on the fin active area; a floating electrode formed on the surfaces of the gate tunneling oxide film and the first oxide film; a inter-gates oxide film formed on the surface of the floating electrode; and a control electrode formed on the surface of the inter-gates oxide film. With the above double-gate flash memory structure, a flash memory element in the present invention improves the scaling down characteristic and the programming and retention characteristic of a flash memory element.
摘要翻译：本发明提供一种闪存元件及其制造方法，该闪存元件及其制造方法通过构成用于改善闪存元件的缩小特性的双栅元件而具有改善的整体存储特性。一种闪存元件包括：形成在硅衬底的表面上的第一氧化物膜; 垂直形成在第一氧化物膜上的鳍状有源区; 在所述鳍式有源区上形成的栅极隧穿氧化物膜; 形成在栅隧穿氧化膜和第一氧化膜的表面上的浮置电极; 在浮置电极的表面上形成的栅极间氧化物膜; 以及形成在栅极间氧化膜的表面上的控制电极。利用上述双栅极闪存结构，本发明中的闪存元件改善了闪存元件的缩放特性以及编程和保持特性。

10. 发明授权

KR100420070B1 이중-게이트 플래쉬 메모리소자 및 그 제조방법 失效
标题翻译： 이중 - 게이트플래쉬메모리소자및그제조방법
公开(公告)号：KR100420070B1
公开(公告)日：2004-02-25
申请号：KR1020020005910
申请日：2002-02-01
申请人： 한국과학기술원
发明人： 이종호
IPC分类号： H01L27/10 , B82Y10/00
摘要： PURPOSE: A dual-gate flash memory device and its manufacturing method are provided to improve the scaling down characteristic of conventional MOS flash memory devices and memory characteristic. CONSTITUTION: A well-type Fin active region(4) having a width of less than 100nm is formed on a bulk silicon wafer(2b) that do not occur a floating body effect and a thermal conductive problem. A tunneling oxide layer(12) is formed on the sidewall. A floating electrode(32) for storing charges is formed.
摘要翻译：目的：提供一种双栅极闪存装置及其制造方法，以改善传统MOS闪存装置的缩小特性和存储特性。构成：在体硅晶片（2b）上形成宽度小于100nm的阱型有源区（4），其不会产生浮体效应和导热问题。隧道氧化层（12）形成在侧壁上。形成用于存储电荷的浮动电极（32）。

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