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    • 7. 发明公开
    • 집적 메모리
    • 集成记忆和加速疲劳测试
    • KR1020040004101A
    • 2004-01-13
    • KR1020030044083
    • 2003-07-01
    • 애질런트 테크놀로지스, 인크.텍사스 인스트루먼츠 인코포레이티드
    • 릭키스쥬겐티맥아담스휴피그레이스제임스더블유퐁존와이랜함랄프에이치
    • G11C11/22
    • G11C29/50G11C11/22G11C2029/5002
    • PURPOSE: An FeRAM(Ferroelectric Random Access Memory) is provided to improve architectures and to permit fatigue testing within commercially expedient times are sought. CONSTITUTION: An FeRAM(100) includes a FeRAM core(110), decoding circuits(130,135), a main control logic(140), a precharge circuit(150), and I/O buffers(160). The FeRAM core(110) contains FeRAM cells for storage of data, and the decoding circuits(130,135) decode or interpret an address signal for read, write, and accelerated fatigue operations accessing specific FeRAM cells in FeRAM core(110). The main control logic(140) controls operation of FeRAM(100) including the read operations, write operations, and accelerated fatigue operations. Precharge circuit(150) and I/O buffers(160) work in cooperation to input data signals for writing to FeRAM core(110) and to output data signals read from FeRAM core.
    • 目的:提供FeRAM(铁电随机存取存储器),以改善架构,并在商业上有利的时间允许疲劳测试。 构成:FeRAM(100)包括FeRAM内核(110),解码电路(130,135),主控制逻辑(140),预充电电路(150)和I / O缓冲器(160)。 FeRAM核心(110)包含用于存储数据的FeRAM单元,并且解码电路(130,135)解码或解释访问FeRAM核心(110)中的特定FeRAM单元的读,写和加速疲劳操作的地址信号。 主控制逻辑(140)控制包括读操作,写操作和加速疲劳操作的FeRAM(100)的操作。 预充电电路(150)和I / O缓冲器(160)协同工作以输入用于写入FeRAM核心(110)的数据信号并输出​​从FeRAM核心读取的数据信号。