专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

KR1020130104430A 멀티-칩 패키지 및 그의 제조 방법 无效
标题翻译：多芯片封装及其制造方法
公开(公告)号：KR1020130104430A
公开(公告)日：2013-09-25
申请号：KR1020120025911
申请日：2012-03-14
申请人： 삼성전자주식회사
发明人： 정진영 , 공도일 , 김해익
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L23/562 , C12M47/02 , H01L21/82 , H01L23/3128 , H01L23/49811 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/48992 , H01L2224/49113 , H01L2224/49421 , H01L2224/73265 , H01L2224/85205 , H01L2224/85399 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： PURPOSE: A multi-chip package and a manufacturing method thereof are provided to prevent the thickness of the multi-chip package from being increased by reducing the thickness of a semiconductor chip with an overhang below the thickness of another semiconductor chip. CONSTITUTION: A first semiconductor chip (120) is arranged on the upper surface of a package substrate (110). The first semiconductor chip has a first bonding pad (122) which is electrically connected to the package substrate. A second semiconductor chip (130) includes an overhang (131) which is more protrusive than the side of the first semiconductor chip and a second bonding pad (132) which is arranged on the overhang. A third semiconductor chip (140) is arranged on the upper surface of the second semiconductor chip to expose the overhang. A first conductive wire (151) electrically connects the second bonding pad to a third bonding pad. A second conductive wire (152) electrically connects the third bonding pad to the package substrate.
摘要翻译：目的：提供一种多芯片封装及其制造方法，以通过以超过另一半导体芯片的厚度的突出来减小半导体芯片的厚度来防止多芯片封装的厚度增加。构成：第一半导体芯片（120）布置在封装衬底（110）的上表面上。第一半导体芯片具有电连接到封装基板的第一焊盘（122）。第二半导体芯片（130）包括比第一半导体芯片的侧面更突出的突出端（131）和布置在突出端上的第二接合焊盘（132）。第三半导体芯片（140）布置在第二半导体芯片的上表面上以暴露突出端。第一导线（151）将第二接合焊盘电连接到第三接合焊盘。第二导线（152）将第三接合焊盘电连接到封装衬底。

2. 发明授权

KR1019960005040B1 반도체 패키지 몰딩 장치 失效
标题翻译：半导体封装成型装置
公开(公告)号：KR1019960005040B1
公开(公告)日：1996-04-18
申请号：KR1019920016336
申请日：1992-09-08
申请人： 삼성전자주식회사
发明人： 이상국 , 김길백 , 최희종 , 김해익
IPC分类号： H01L21/56
摘要： The apparatus consists of an upper molding die and a lower molding die. A rot is formed in the center of the upper molding die, some of runners are connected to the rot, several runner bars are connected to the respective runners, and two supplementary cavities are formed on both sides of the end of the respective runner bars. Also, lead frames for mounting semiconductor chips are installed in the respective cavities between the upper and lower molding dies. The semiconductor chip packages are formed by filling the cavities with epoxy resin through rot, runners, runner bars and gates. Formation of the supplementary cavities prevents the faulty of wire sweeping, die pad tilting, etc. from generating.
摘要翻译：该设备包括上模压模和下成型模。在上模塑件的中心形成腐蚀，一些流道与腐烂连接，几个流道杆连接到相应的流道，并且在相应流道杆的端部的两侧上形成两个辅助空腔。此外，用于安装半导体芯片的引线框安装在上模和下模之间的相应空腔中。通过腐蚀，流道，流道条和浇口用环氧树脂填充空腔来形成半导体芯片封装。辅助空腔的形成可以防止金属丝清扫，管芯焊盘倾斜等发生故障。

3. 发明公开

KR1020070070764A ＢＧＡ 패키지 몰딩 장치 无效
标题翻译： BGA封装模具
公开(公告)号：KR1020070070764A
公开(公告)日：2007-07-04
申请号：KR1020050133618
申请日：2005-12-29
申请人： 삼성전자주식회사
发明人： 김해익
IPC分类号： H01L23/28 , H01L21/60 , H01L21/56
CPC分类号： H01L21/67126 , B29C45/34 , H01L21/565 , H01L23/28
摘要： An apparatus for molding a BGA package is provided to prevent a ball land from being contaminated by molding resin flowing out from an air vent by guiding flash of the molding resin to a position where a ball land is not formed. A cavity(113) is formed in at least one of an upper die(111) or a lower die, sealing a predetermined portion of the inside of a ball land on one surface of a substrate on which a semiconductor chip is mounted. Molding resin is introduced through a resin inflow hole(115) connected to the cavity. The air in the cavity is exhausted through an air vent(117) connected to the cavity. The air vent includes a first section(118) extending outward from at least one corner of the cavity and a second section(119) crossing the first section. The air vent can be formed in the rest of the corners except the resin inflow hole.
摘要翻译：提供了一种用于模制BGA封装的装置，用于通过将模制树脂的闪光引导到没有形成球场的位置来防止球场被从通气孔流出的模制树脂污染。在上模（111）或下模中的至少一个中形成空腔（113），在其上安装有半导体芯片的基板的一个表面上密封球台内部的预定部分。通过连接到空腔的树脂流入孔（115）引入成型树脂。空腔中的空气通过连接到空腔的通风口（117）排出。排气孔包括从空腔的至少一个角向外延伸的第一部分（118）和与第一部分交叉的第二部分（119）。除了树脂流入孔之外，排气孔可以形成在其余的角部。

4. 发明授权

KR100275713B1 반도체 칩 제조용 절단펀치 失效
标题翻译：切割冲孔用于制造半导体芯片
公开(公告)号：KR100275713B1
公开(公告)日：2001-01-15
申请号：KR1019920021642
申请日：1992-11-18
申请人： 삼성전자주식회사
发明人： 최희종 , 김길백 , 김해익
IPC分类号： H01L21/50 , H01L23/50
摘要： PURPOSE: A cutting punch for fabricating a semiconductor chip is provided to improve punching efficiency of a punch by forming front blade portions with different lengths in a cutting punch for cutting an unnecessary portion of a semiconductor package or a lead frame. CONSTITUTION: A plurality of front blade portions(22a) are formed at a predetermined interval from a lower end portion of a main body(22). The front blade portions(22a) have different lengths. In a cutting process, a semiconductor chip is loaded on a die(21). A punch(20) is fallen by a predetermined elevation portion. A bur adhered on an outer circumference of a lead frame(40) and a packaged chip is cut by falling the punch(20). The front blade portions(22a) have different cutting forces since the front blade portions(22a) has different lengths.
摘要翻译：目的：提供一种用于制造半导体芯片的切割冲头，以通过在用于切割半导体封装或引线框架的不需要部分的切割冲头中形成具有不同长度的前刀片部分来提高冲头的冲压效率。构成：从主体（22）的下端部以规定的间隔形成有多个前叶片部（22a）。前刀片部分（22a）具有不同的长度。在切割过程中，将半导体芯片装载在模具（21）上。冲头（20）被预定的高度部分掉落。附着在引线框架（40）的外周上的毛坯，并且通过使冲头（20）落下来切割封装的芯片。前刀片部分22a具有不同的切割力，因为前刀片部分22a具有不同的长度。

5. 发明授权

KR100101715B1 반도체 패키지 몰딩 장치 失效
公开(公告)号：KR100101715B1
公开(公告)日：1996-07-05
申请号：KR1019920016336
申请日：1992-09-08
申请人： 삼성전자주식회사
发明人： 이상국 , 김길백 , 최희종 , 김해익
IPC分类号： H01L21/56

6. 发明公开

KR1019940008025A 반도체 패키지 몰딩 장치 失效
公开(公告)号：KR1019940008025A
公开(公告)日：1994-04-28
申请号：KR1019920016336
申请日：1992-09-08
申请人： 삼성전자주식회사
发明人： 이상국 , 김길백 , 최희종 , 김해익
IPC分类号： H01L21/56
摘要： 몰딩수지를 가압 성형하여 반도체패키지를 형성하는 반도체 패키지 몰딩장치에서 다수개의 런너에 런너바, 게이트 및 캐비티가 순차적으로 연결되어 있다. 이때 상기 런너에서 비교적 먼거리에 위치하여 EMC가 가장 늦게 충진되는 런너바의 끝단 양측에 보조 캐비티를 소정의 크기로 추가로 형성하였다.
따라서, 상기 반도체 패티지 몰딩공정시 가장 늦게 EMC가 충진되는 캐비티의 일측에 보조 캐비티로 공간이 형성되어 있으므로, 캐비티로의 EMC의 유입속도가 급격히 변화되지 않는다. 따라서 몰딩 공정시 와이어 스위핑이나 다이패드 틸팅이 발생하지 않아 반도체 장치의 수율 및 신뢰성을 향상시킬수 있다.
또한 EMC의 점도가 증가하여 반도체 패키지 몸체에 발생되는 불완전 몰딩이나 기포등의 외관 불량을 상기 보조 캐비티내에 형성되도록 하여 패키지 몸체의 외관 불량을 방지하여 반도체 장치의 수율 및 신뢰성을 향상시킬 수 있다.

7. 发明公开

KR1020080058015A 돌출부에 의한 체결구조를 포함하는 메모리 카드 无效
标题翻译：具有组合结构的记忆卡
公开(公告)号：KR1020080058015A
公开(公告)日：2008-06-25
申请号：KR1020060132031
申请日：2006-12-21
申请人： 삼성전자주식회사
发明人： 김일기 , 김해익
IPC分类号： H01L23/02 , H01L23/28
CPC分类号： H01L2224/48091 , H01L2924/181 , H01L2924/1815 , H01L2924/00014 , H01L2924/00012 , G06K19/0772 , H01L23/28 , H01L25/074
摘要： A memory card having a combining structure with a protrusion is provided to prevent a card main body from being detached from a base card due to a decrease of an adhesive strength of an adhesive by combining and fixing the card main body to the base card using a protrusion formed on the base card without use of the adhesive. A memory card(100) having a combining structure with a protrusion includes: a card main body(150) and a base card(130). The card main body includes a semiconductor chip(110) enclosed in a mold portion(114) with a molding material and a printed circuit board(120) having one surface on which the semiconductor chip is mounted and the other surface on which a plurality of external contact terminals(124) are formed. The base card includes an inserting portion(134) having one side into which the card main body is inserted and the first protrusion(140) which fixes the card main body to lower ends of both sides of the inserting portion.
摘要翻译：提供了具有与突起的组合结构的存储卡，以防止卡主体由于通过将卡主体组合并固定到基卡而使粘合剂的粘合强度降低而与基卡分离，使用突起形成在基卡上而不使用粘合剂。具有与突起的组合结构的存储卡（100）包括：卡主体（150）和基卡（130）。卡主体包括封装在具有成型材料的模具部分（114）中的半导体芯片（110）和具有一个表面的印刷电路板（120），半导体芯片安装在其上，多个形成外部接触端子（124）。该基座卡包括一个插入部分（134），该插入部分（134）具有卡主体插入其中的一侧，以及第一凸起（140），其将卡主体固定到插入部分两侧的下端。

8. 发明公开

KR1020070012965A 솔더 볼 및 솔더 페이스트를 이용한 적층 패키지 无效
标题翻译：堆叠包装使用焊球和焊膏
公开(公告)号：KR1020070012965A
公开(公告)日：2007-01-30
申请号：KR1020050067249
申请日：2005-07-25
申请人： 삼성전자주식회사
发明人： 최진아 , 김해익
IPC分类号： H01L23/48 , H01L21/60 , H01L23/12
CPC分类号： H01L2924/181 , H01L2924/00012
摘要： A stack package using a solder ball is provided to prevent bridges from being formed between outer leads of unit packages by reflowing a solder ball or solder paste so that the outer lead of a lower unit package is bonded to the outer lead of an upper unit package. A first concave groove(32) concaved downward is formed in a shoulder part(23) of a lower unit package(30a). An upper unit package(30b) is disposed on the lower unit package to position a foot part(25) in the shoulder part of the lower unit package. An adhesion layer(40) is formed between the body of the lower unit package and the body of the upper unit package. A solder ball(50) is formed on the first concave part and is reflowed to bond the shoulder part of the lower unit package to the foot part of the upper unit package. A second concave groove(34) is formed in the foot part of the upper unit package, concaved upward to correspond to the first concave groove. The solder ball is interposed between the first concave groove and the second concave groove.
摘要翻译：提供使用焊球的堆叠封装，以通过回流焊球或焊膏来防止在单元封装的外引线之间形成桥，使得下单元封装的外引线结合到上单元封装的外引线。在下单元封装（30a）的肩部（23）中形成有向下凹入的第一凹槽（32）。上单元封装（30b）设置在下单元封装上，以将脚部（25）定位在下单元封装的肩部中。在下单元封装的主体和上单元封装的本体之间形成粘合层（40）。焊球（50）形成在第一凹部上并被回流焊接以将下单元封装的肩部部分结合到上单元封装的脚部。第二凹槽（34）形成在上单元封装的底部中，向上凹入以对应于第一凹槽。焊球介于第一凹槽和第二凹槽之间。

9. 发明公开

KR1020040026235A 완충부가 형성된 볼 그리드 어레이 패키지용 인쇄회로기판스트립 无效
标题翻译：带缓冲单元的球形阵列打印电路板条
公开(公告)号：KR1020040026235A
公开(公告)日：2004-03-31
申请号：KR1020020057611
申请日：2002-09-23
申请人： 삼성전자주식회사
发明人： 김해익 , 김형석
IPC分类号： H01L23/12
摘要： PURPOSE: A printed circuit board strip for a ball grid array(BGA) package with a buffer unit is provided to control damage to a photo solder resist(PSR) layer or generation of flash caused by a thickness difference by maintaining a uniform thickness of the upper surface of the printed circuit board strip so that the force of clamping mold dies is distributed to the whole printed circuit board strip. CONSTITUTION: The substrate body is prepared. A chip mounting region(23) is formed on the substrate body to mount a semiconductor chip. A package region(27) includes the chip mounting region in which a semiconductor chip mounting part is encapsulated by molding resin. A plurality of printed circuit board substrates include the substrate body, the chip mounting region and the package region. A side rail(16) interconnects the plurality of printed circuit board substrates, respectively. A tie bar(14) connects the plurality of printed circuit board substrates with the side rail, extending from a part of the substrate body to the side rail. A buffer unit(30) is discontinuously formed along the outside of the package region. The buffer unit includes the first buffer pattern(32) and the first buffer unit(31). The first buffer pattern is formed along the outside of the package region. The first buffer unit is composed of the PSR layer covering the first buffer pattern.
摘要翻译：目的：提供一种用于具有缓冲单元的球栅阵列（BGA）封装的印刷电路板条，以通过保持均匀的厚度来控制对光阻抗层（PSR）层的损伤或由厚度差产生的闪光印刷电路板条的上表面，使得夹紧模具的力分布到整个印刷电路板条。构成：制备基体。芯片安装区域（23）形成在基板主体上以安装半导体芯片。封装区域（27）包括通过模制树脂封装半导体芯片安装部分的芯片安装区域。多个印刷电路板基板包括基板主体，芯片安装区域和封装区域。侧轨（16）分别互连多个印刷电路板基板。连杆（14）将多个印刷电路板基板与侧轨连接，从基板主体的一部分延伸到侧轨。缓冲单元（30）沿着封装区域的外部不连续地形成。缓冲单元包括第一缓冲图案（32）和第一缓冲单元（31）。第一缓冲图案沿着封装区域的外侧形成。第一缓冲单元由覆盖第一缓冲图案的PSR层组成。

10. 发明公开

KR1019940012552A 반도체 칩 제조용 절단펀치 失效
标题翻译：半导体芯片制造的切割冲头
公开(公告)号：KR1019940012552A
公开(公告)日：1994-06-23
申请号：KR1019920021642
申请日：1992-11-18
申请人： 삼성전자주식회사
发明人： 최희종 , 김길백 , 김해익
IPC分类号： H01L21/50 , H01L23/50
摘要： 본 발명은 반도체 칩 제조용 절단장치를 개시한다.
본 발명은 다이와 결합되어 반도체 칩의 몰드 패키지에 부착된 버 또는 리드 프레임을 절단하는 반도체 칩 제조용 절단펀치에 관한 것으로, 펀치의 본체와 상기 본체의 하단부에 상호 소정간격 이격 되며 본체로부터 연장되는 길이가 다르게 형성된 전단날부를 구비하여 절단되는 부위에 따라 가하여 지는 전단력이 다르게 된 것을 그 특징이 있으며 이는 전단날부에 의해 전단된 스크랩이 부착되는 것을 방지할 수 있고 펀치의 펀칭효율을 향상시킬수 있는 이점을 가진다.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式