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81. 发明授权

KR101100958B1 불휘발성 메모리 장치 有权
标题翻译：非易失性存储器件
公开(公告)号：KR101100958B1
公开(公告)日：2011-12-29
申请号：KR1020100087050
申请日：2010-09-06
申请人： 에스케이하이닉스 주식회사
发明人： 조용덕
IPC分类号： G11C16/06 , G11C16/08 , G11C16/32
CPC分类号： G11C29/84 , G11C29/70 , G11C29/781
摘要： PURPOSE: A non volatile memory device is provided to improve integration by sharing a common input/output line. CONSTITUTION: In a non volatile memory device, a normal page buffer part(120) transmits data to a normal memory cell array(110). The normal page buffer part senses data in reading. . A normal column decoder(140) decodes a column address signals and outputs a pre-decoding signal. A redundancy memory cell array(210) comprises a plurality of memory cells A redundancy page buffer part(220) senses data in reading. A redundancy column decoder(230) generates a plurality of redundancy column address decoding signals. A redundancy pre-decoder(240) outputs a pre-decoding signal. A redundancy circuit(300) outputs a normal control clock, a redundancy control clock, and a redundancy column address signals.
摘要翻译：目的：提供一种非易失性存储器件，通过共享一个公共输入/输出线来提高集成度。构成：在非易失性存储器件中，正常页缓冲器部分（120）将数据发送到正常存储单元阵列（110）。正常页面缓冲部分检测读取中的数据。。正常列解码器（140）解码列地址信号并输出预解码信号。冗余存储单元阵列（210）包括多个存储单元，冗余页缓冲器部分（220）感测读取中的数据。冗余列解码器（230）产生多个冗余列地址解码信号。冗余预解码器（240）输出预解码信号。冗余电路（300）输出正常控制时钟，冗余控制时钟和冗余列地址信号。

82. 发明公开

KR1020100073622A 반도체 메모리 장치의 리던던시 어드레스 판별 회로 无效
标题翻译：半导体存储器的冗余地址确定电路
公开(公告)号：KR1020100073622A
公开(公告)日：2010-07-01
申请号：KR1020080132338
申请日：2008-12-23
申请人： 에스케이하이닉스 주식회사
发明人： 황선영 , 박상일
IPC分类号： G11C8/04 , G11C29/00
CPC分类号： G11C29/787 , G11C29/83 , G11C29/84
摘要： PURPOSE: A redundancy address determination circuit of a semiconductor memory device is provided to increase the operation speed of the semiconductor memory device by increasing an output response speed. CONSTITUTION: A redundancy address determination circuit includes a plurality of address-fuse signal generators(101-106) and a determination signal generator(200). The determination signal generator generates the determination signal. An address-fuse signal generator outputs the address signal or inverted address signal as an address-fuse signal. A determination signal generator disables or enables the determination signal according to the address-fuse signal.
摘要翻译：目的：提供半导体存储器件的冗余地址确定电路，通过增加输出响应速度来提高半导体存储器件的操作速度。构成：冗余地址确定电路包括多个地址熔丝信号发生器（101-106）和确定信号发生器（200）。确定信号发生器产生确定信号。地址熔丝信号发生器输出地址信号或反相地址信号作为地址熔丝信号。确定信号发生器根据地址熔丝信号禁止或使能确定信号。

83. 发明公开

KR1020080099622A 리던던시 회로 失效
标题翻译：冗余电路
公开(公告)号：KR1020080099622A
公开(公告)日：2008-11-13
申请号：KR1020070045408
申请日：2007-05-10
申请人： 에스케이하이닉스 주식회사
发明人： 윤혁수
IPC分类号： G11C29/00
CPC分类号： G11C29/84
摘要： A redundancy circuit is provided to receive a comparison signal of the outside input address and fuse address and output respective determined result of the received signal to the predetermined timing. In a redundancy circuit, a comparison receiving unit receives a plurality of comparison signals which are result comparison of a plurality of fuse addresses and plurality of low(row) addresses and receives the fuse activating signal(410) in parallel. A redundancy control signal generating unit(420) supplies a redundancy control signal by controlling a transmission path of the output signal of the comparison signal receiving unit according to the signal level of the row address activation signal. A comparison signal receiving unit receives the fuse activation signal and a plurality of comparison signals during an activation period for row address signal.
摘要翻译：提供冗余电路以接收外部输入地址和熔丝地址的比较信号，并将接收信号的相应确定结果输出到预定定时。在冗余电路中，比较接收单元接收多个比较信号，这些比较信号是多个熔丝地址和多个低（行）地址的比较结果，并且并行地接收熔丝激活信号（410）。冗余控制信号生成单元（420）根据行地址激活信号的信号电平，控制比较信号接收单元的输出信号的传输路径，提供冗余控制信号。比较信号接收单元在行地址信号的激活周期期间接收保险丝激活信号和多个比较信号。

84. 发明授权

KR100566848B1 불휘발성 반도체 기억 장치 有权
标题翻译：非易失性半导体存储器件，能够在短时间内实现有效的编程操作和擦除操作
公开(公告)号：KR100566848B1
公开(公告)日：2006-04-03
申请号：KR1020040073744
申请日：2004-09-15
申请人： 가부시끼가이샤 르네사스 테크놀로지
发明人： 미따니히데노리 , 니따후미히꼬 , 야마우찌다다아끼 , 오구라다꾸
IPC分类号： G11C16/14 , G11C16/16 , G11C16/02
CPC分类号： G11C29/84 , G11C16/10 , G11C16/16 , G11C16/22 , G11C16/30 , G11C16/344
摘要： 펄스 인가 횟수(n)가 12회까지는 전반 펄스로서 펄스 폭이 고정인 2ms로 설정되고, 또한 1회마다 펄스 전압이 증가된다. 또한, 후반 펄스로서 전압이 최대 전압에 도달하기까지는 3ms의 고정 펄스 폭이며, 또한 1회마다 펄스 전압이 증가된다. 최대 전압 도달 이후에는 먼저 펄스 폭 3ms로 2회 펄스가 인가되고, 다음에 최대 전압에서 펄스 폭 4ms로 2회 펄스가 인가되며, 이어 최대 전압에서 펄스 폭 5ms로 2회 펄스가 인가된다. 최대 전압 도달 이후에도 임계치 전압의 시간적 변화를 리니어로 근접시킬 수 있다.
따라서, 프로그램 동작이나 소거 동작을 단시간에 또한 효율적으로 수행할 수 있는 불휘발성 반도체 기억 장치를 제공할 수 있다.
불휘발성 반도체 기억 장치, 메모리 블록, 전원 회로, 제어부, 소거 펄스

85. 发明授权

KR100535648B1 블럭 선택 회로 失效
标题翻译：块选择电路
公开(公告)号：KR100535648B1
公开(公告)日：2005-12-08
申请号：KR1020040027099
申请日：2004-04-20
申请人： 에스케이하이닉스 주식회사
发明人： 윤상식
IPC分类号： G11C8/12
CPC分类号： G11C29/785 , G11C29/84
摘要： 본 발명은 블럭 선택 회로에 관한 것으로, 퓨즈 컷 상태와 외부 어드레스에 따라 외부 어드레스가 리페어 어드레스인지를 판단하는 퓨즈 블럭으로부터 출력되는 판단 신호보다 늦거나 같게 기준 신호가 출력되도록 퓨즈 블럭을 모사하여 기준 퓨즈 블럭을 구성하고, 기준 신호를 이용하여 판단 신호보다 늦게 스페어 로우 인에이블 신호를 생성함으로써 지연부가 제거되어 블럭 선택 회로의 속도를 향상시킬 수 있고, 공정, 온도, 동작 전원등이 변화에 따라 퓨즈 블럭으로부터의 판단 신호의 출력 속도가 변화되더라도 기준 퓨즈 블럭 또한 비슷하게 변화되므로 동작의 안정성을 확보할 수 있는 블럭 선택 회로가 제시된다.

86. 发明公开

KR1020050101866A 블럭 선택 회로 失效
标题翻译：块选择电路
公开(公告)号：KR1020050101866A
公开(公告)日：2005-10-25
申请号：KR1020040027099
申请日：2004-04-20
申请人： 에스케이하이닉스 주식회사
发明人： 윤상식
IPC分类号： G11C8/12
CPC分类号： G11C29/785 , G11C29/84 , G11C29/787 , G11C8/12 , G11C2229/763
摘要： Provided is directed to a block selection circuit, comprising a reference fuse block by copying fuse blocks to output a reference signal later than or at the same time to decision signals which are outputted from fuse blocks which distinguish whether an external address is a repair address or not according to fuse cutting states and an external address, capable of improving speed of the block selection circuit by removing delay units by means of generating a spare row enable signal later than decision signals using the reference signal, and available to assure stability of an operation because the reference fuse block is similarly changeable, although outputting speeds of decision signals from fuse blocks are variable according to a process, a temperature, a driving voltage, and so on.

87. 发明公开

KR1020030000590A 시프트 리던던시 회로를 갖는 반도체 메모리 장치 失效
标题翻译：具有移位冗余电路的半导体存储器件
公开(公告)号：KR1020030000590A
公开(公告)日：2003-01-06
申请号：KR1020010036626
申请日：2001-06-26
申请人： 삼성전자주식회사
发明人： 김진성 , 곽종택 , 곽진호 , 이선민
IPC分类号： G11C29/00
CPC分类号： G11C29/812 , G11C8/10 , G11C29/84
摘要： PURPOSE: A semiconductor memory device having a shift redundancy circuit is provided reduce a size of chip by using the minimum number of fuse. CONSTITUTION: A memory cell array block(200) is formed with a plurality of memory cell arrays(102,104,106,108,110,112) in order to store data. A column decoder block(300) is formed with a plurality of column decoders(114,116,118,120,122,124). A sense amplifier and write buffer block(400) are formed with a plurality of sense amplifiers and write buffers(126,128,130,132,134,136) in order to amplify the data. A fuse box(800) has a function for storing access information for memory blocks. A decoder block(700) is formed with a plurality of decoders(156,158,160,162,164) in order to decode output signals of the fuse box(800). A control signal generation circuit block(600) is formed with a plurality of control signal generation circuits(148,150,152,154). A shift redundancy circuit block(500) is formed with a plurality of shift redundancy circuits(138,140,142,144,146).
摘要翻译：目的：提供具有移位冗余电路的半导体存储器件，通过使用最小数量的保险丝来减小芯片的尺寸。构成：为了存储数据，存储单元阵列块（200）形成有多个存储单元阵列（102,104,106,108,110,112）。列解码器块（300）形成有多个列解码器（114,116,118,120,122,124）。读出放大器和写入缓冲器块（400）形成有多个读出放大器和写入缓冲器（126,128,130,132,134,136），以便放大数据。保险丝盒（800）具有用于存储存储块的存取信息的功能。解码器块（700）形成有多个解码器（156,158,160,162,164），以便解码保险丝盒（800）的输出信号。控制信号生成电路块（600）形成有多个控制信号生成电路（148,150,152,154）。移位冗余电路块（500）形成有多个移位冗余电路（138,140,142,144,146）。

88. 发明公开

KR1020010085367A 반도체 집적 회로 无效
标题翻译：半导体集成电路
公开(公告)号：KR1020010085367A
公开(公告)日：2001-09-07
申请号：KR1020010006701
申请日：2001-02-12
申请人： 후지쯔 가부시끼가이샤
发明人： 이케다히토시 , 후지오카신야
IPC分类号： G11C29/00
CPC分类号： G11C29/83 , G11C8/10 , G11C29/84
摘要： PURPOSE: To reduce power consumption in the operation of a redundant circuit more than conventional one in a semiconductor integrated circuit having a redundant circuit relieving a memory cell. CONSTITUTION: This circuit is provided with a memory cell block, a first decoder 16, and a second decoder 18. The memory cell block has plural memory cell strings in which memory cells are arranged in the one direction and a redundant memory cell string for relieving defects of these memory cell strings. The first decoder 16 selects any of memory cell blocks, the second decoder 18 selects any of memory cell strings in the memory cell block. Operation of the second decoder 18 being not used for decoding of the redundant memory cell string is stopped at the time of operation of the redundant memory cell string. As a needless circuit is not operated, power consumption can be reduced at the time of operation of the redundant memory cell string.
摘要翻译：目的：减少冗余电路的功耗，比具有缓冲存储单元的冗余电路的半导体集成电路中的传统功耗更大。构成：该电路设置有存储单元块，第一解码器16和第二解码器18.存储单元块具有多个存储单元串，其中存储单元沿一个方向布置，并且用于缓解的冗余存储单元串这些记忆单元串的缺陷。第一解码器16选择存储单元块中的任何一个，第二解码器18选择存储单元块中的任何存储单元串。在冗余存储单元串的操作时停止不用于冗余存储单元串的解码的第二解码器18的操作。当不必要的电路不工作时，在冗余存储单元串的操作时可以减少功耗。

89. 发明公开

KR1020010069997A 반도체 메모리 장치 失效
标题翻译：半导体存储器
公开(公告)号：KR1020010069997A
公开(公告)日：2001-07-25
申请号：KR1020000042177
申请日：2000-07-22
申请人： 닛폰 덴키 가부시끼 가이샤 , 르네사스 일렉트로닉스 가부시키가이샤
发明人： 오제키세이지
IPC分类号： G11C29/00
CPC分类号： G11C29/84
摘要： PURPOSE: To improve an access time when access is switched from a redundant cell to a normal cell. CONSTITUTION: In a semiconductor memory which generates a YREDB signal meaning use/nonuse of a redundant cell based on an address signal externally inputted and controls a decoder circuit for a normal cell by this signal so that it is made inactive at the time of using a redundant cell and it is activated at the time of nonuse of a redundant cell, the device has plural redundant circuits 10 which are activated when an inputted address signal is a signal corresponding to a redundant cell and which are made inactive when an inputted address signal is a signal corresponding to a normal cell, a logic circuit section which activates a YREDB signal when all redundant circuits are in an inactive state and makes the YREDB signal an inactive state when any of redundant circuits is in an active state, and an one shot pulse generating circuit 11 which activates forcedly the YREDB signal synchronizing with transition of a clock signal used for timing at which an address signal is inputted when access is switched from a redundant cell to a normal cell.
摘要翻译：目的：提高访问从冗余单元切换到正常单元的访问时间。构成：在基于外部输入的地址信号生成表示使用/不使用冗余单元的YREDB信号的半导体存储器中，通过该信号控制用于正常单元的解码器电路，使得在使用冗余单元，并且在不使用冗余单元时被激活，该设备具有多个冗余电路10，当输入的地址信号是与冗余单元相对应的信号时被激活，并且当输入的地址信号为与正常单元相对应的信号，当所有冗余电路处于非活动状态时激活YREDB信号并且当任何冗余电路处于活动状态时使YREDB信号为非活动状态的逻辑电路部分和单次脉冲发生电路11，其强制地激活YREDB信号，同步与用于输入地址信号的定时的时钟信号的转换 ess从冗余单元切换到正常单元。

90. 发明授权

KR100290696B1 고속 동작이 가능한 용장 셀을 포함하는 반도체 기억 장치 失效
标题翻译：具有高速操作且包括冗余电池的半导体存储器件
公开(公告)号：KR100290696B1
公开(公告)日：2001-05-15
申请号：KR1019990004049
申请日：1999-02-05
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 쯔지다까하루 , 오오이시쯔까사 , 가또히로시 , 도미시마시게끼 , 시마노히로끼
IPC分类号： G11C29/00
CPC分类号： G11C29/84 , G11C29/844
摘要： 고속화또한효율적으로치환가능한반도체기억장치를제공한다. 본발명의반도체기억장치에서는, 용장(redundancy) 판정회로(20)의용장판정과독립적으로, 어드레스신호를디코드한결과에응답하여대응하는노멀블럭에서의워드선을선택상태로하는워드선활성화신호 (서브디코드신호)를활성화한다. WL 드라이버(4)는노멀블럭에서의워드선을선택하는드라이버부분과, 용장블럭에서의스페어워드선을선택하는드라이버부분을구비한다. 용장판정회로(20)에서의용장판정의결과, 용장미사용인경우, 활성화한서브디코드신호를비활성화한다. 용장판정의결과가용장사용인경우, 활성화한서브디코드신호를이용하여대응하는워드선을선택상태로한다.

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