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71. 发明授权

KR100321594B1 반도체 장치 有权
标题翻译：半导体器件
公开(公告)号：KR100321594B1
公开(公告)日：2002-03-18
申请号：KR1019990012041
申请日：1999-04-07
申请人： 후지쯔 가부시끼가이샤
发明人： 가또다까히로
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/12
CPC分类号： H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/05556 , H01L2224/05557 , H01L2224/05599 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/14 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： 패드에작용하는응력에대하여강한구조로하면서, 패드와와이어의접합강도를높일수 있는반도체장치를제공한다. 칩에형성된배선(8)과그 배선(8)에대하여층간막(7)을개재하여배치되어본딩와이어(6)를접합하는패드(3)가콘택트(9)를통하여접속되어있다. 그리고, 패드(3)의주변부에콘택트(9)가형성되고, 패드(3)의중앙부에와이어(6)를접합하는영역에대응하는수의콘택트(9)가형성된다.
摘要翻译：半导体器件包括半导体芯片和形成在芯片上的布线。层间膜位于布线上。衬垫位于层间膜上，并且通过从布线延伸穿过层间膜的触点连接到布线。触点包括位于焊盘周边附近的第一组触点和位于焊盘中心附近的第二组焊盘。通过限制触点的数量和布置，焊盘允许焊盘和布线之间以及焊盘和接合线之间的牢固连接。

72. 发明授权

KR100297451B1 반도체 패키지 및 그의 제조 방법 失效
标题翻译：半导体封装及其制造方法
公开(公告)号：KR100297451B1
公开(公告)日：2001-11-01
申请号：KR1019990027041
申请日：1999-07-06
申请人： 삼성전자주식회사
发明人： 정명기 , 최희국 , 이상엽
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L21/3043 , H01L21/78 , H01L23/3171 , H01L23/3178 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/06136 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/4899 , H01L2224/73265 , H01L2224/85399 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , Y10S438/977 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： 본발명은반도체패키지및 그의제조방법에관한것으로, 센터패드형반도체칩의전극패드에서인출된본딩와이어가반도체칩의모서리에접촉하여전기적쇼트가발생하는것을방지하기위하여, 본딩와이어가접촉하게되는반도체칩의활성면의모서리부분에폴리이미드또는에폭시계열의플라스틱수지로형성된절연층을갖는반도체칩을이용한반도체패키지및 그의제조방법을제공한다. 따라서, 절연층이형성된반도체칩의활성면의모서리부분에본딩와이어가접촉하더라도전기적쇼트현상은발생하지않는다.
摘要翻译：半导体封装和制造方法可以防止由于接合半导体芯片的边缘的接合线导致的电气短路。在半导体芯片的边缘处的绝缘区域防止短路。用于形成绝缘区域的一种方法在晶片的划线区域上留下聚酰亚胺层，并穿过聚酰亚胺层。为了避免切屑，切割使用细磨刀片和缓慢的切割速度。另一种方法是从划线区域去除聚酰亚胺，并在半导体芯片的边缘上形成绝缘区域。封装方法可以在切割晶片之后并且将分离的芯片附接到基板之后将绝缘区域沉积在半导体芯片上。或者，绘图或印刷可以在晶片上施加绝缘材料。切割过程然后切割绝缘材料和晶片，并在每个分离的芯片上留下绝缘区域。可以在划线区域形成凹槽，然后在沿着凹槽切割之前填充绝缘材料。结果，从凹槽内部的绝缘材料延伸到分离的半导体芯片的侧面上。如果在晶片的背面研磨之前形成槽，则绝缘区域可以覆盖芯片的侧面。绝缘材料通常是能够切割而不会发生切屑的环氧树脂。

73. 发明公开

KR1020010090574A 스크라이브 라인 상에 뱅크를 구비하는 반도체 웨이퍼 无效
标题翻译：半导体晶圆及其制造方法
公开(公告)号：KR1020010090574A
公开(公告)日：2001-10-18
申请号：KR1020010015761
申请日：2001-03-26
申请人： 르네사스 일렉트로닉스 가부시키가이샤
发明人： 후지이모유루
IPC分类号： H01L21/304
CPC分类号： H01L23/3171 , H01L21/78 , H01L2224/02381 , H01L2224/05001 , H01L2224/05027 , H01L2224/05552 , H01L2224/05556 , H01L2224/05571 , H01L2224/16 , H01L2924/01078
摘要： PURPOSE: To prevent grinding chips, which are produced during when the back is ground, from polluting an electrode pad in a back-grinding step for adsorbing a water surface, by using a simple method such as vacuum suction. CONSTITUTION: The method of manufacturing a semiconductor wafer and the semiconductor wafer manufactured by the method are characterized to include as a step for manufacturing a semiconductor wafer, in the back grinding step, the surface of a polyimide film formed wafer 2 is sucked after a polyimide film forming step for removing a polyimide film 8 on large parts of scrub lines 7 and a region between the scrub lines 7 and electrode pads 5 being adjacent to the scrub lines 7. In this step, the pattern of the polyimide film 8 in the polyimide film forming step includes banks 17b, by which the pattern of the polyimide film 8 in the polymide film forming step divides the scrub lines 7 near the intersections of the scrub lines 7 provided in a lattice form, so as to prevent the entry of grinding chips 14 generated, when the back is ground.
摘要翻译：目的：为了防止在背面研磨时产生的研磨屑，通过使用真空抽吸等简单方法，在用于吸附水面的背面研磨工序中污染电极焊盘。构成：通过该方法制造半导体晶片和半导体晶片的方法的特征在于，作为制造半导体晶片的步骤，在背面研磨工序中，将聚酰亚胺膜形成晶片2的表面在聚酰亚胺在擦洗线7的大部分上除去聚酰亚胺膜8的膜形成步骤以及与擦洗线7相邻的擦洗线7和电极焊盘5之间的区域。在该步骤中，聚酰亚胺膜8在聚酰亚胺膜形成步骤包括堤17b，聚酰亚胺膜形成步骤中的聚酰亚胺膜8的图案在格栅形式的擦洗线7的交叉点附近划分擦洗线7，以防止磨屑 14产生，当背面被磨碎。

74. 发明公开

KR1020010076412A 반도체 구조의 구리 금속화에 적합한 아키텍처 및 와이어본딩 방법 无效
标题翻译：用于在半导体结构中进行铜金属化的线接合和结构
公开(公告)号：KR1020010076412A
公开(公告)日：2001-08-11
申请号：KR1020010003362
申请日：2001-01-20
申请人： 알카텔-루센트 유에스에이 인코포레이티드
发明人： 치티페디세일러시 , 멀천트세일러시멘신 , 로이프라딥커머
IPC分类号： H01L21/60
CPC分类号： H01L24/48 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05546 , H01L2224/05556 , H01L2224/05624 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48699 , H01L2224/48724 , H01L2224/48799 , H01L2224/48824 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2224/78 , H01L2924/00 , H01L2924/00015
摘要： PURPOSE: A structure and a method for enabling use of wire bonding are provided to perform connection to the outside by Cu wiring and to control corrosion and a wire bonding in integrated circuits. CONSTITUTION: The integrated circuit device comprises a first segment of conductor predominantly comprising Cu. The conductor segment is formed on an integrated circuit structure and includes a contact region for electrical connection. A conductive barrier layer is formed about the contact region for preventing migration of Cu atoms from the contact region to other conductor material and an Al bond pad are formed about the barrier layer such that the barrier layer is disposed between the contact region and the bond pad.
摘要翻译：目的：提供一种能够使用引线接合的结构和方法，以通过Cu布线实现与外部的连接，并且控制集成电路中的腐蚀和引线接合。构成：集成电路器件包括主要包含Cu的导体的第一段。导体段形成在集成电路结构上并且包括用于电连接的接触区域。围绕接触区域形成导电阻挡层，用于防止Cu原子从接触区域迁移到其它导体材料，并且在阻挡层周围形成Al键合焊盘，使得阻挡层设置在接触区域和接合焊盘。

75. 发明公开

KR1020010076331A 반도체 장치 및 그 제조 방법, 회로기판 및 전자기기 有权
标题翻译：半导体器件及其制造方法，电路板作为电子设备
公开(公告)号：KR1020010076331A
公开(公告)日：2001-08-11
申请号：KR1020010002836
申请日：2001-01-18
申请人： 세이코 엡슨 가부시키가이샤
发明人： 하나오카테루나오 , 와다켄지 , 하시모토노부아키 , 이토하루키 , 우메츠카즈시게 , 마츠시마후미아키
IPC分类号： H01L21/768
CPC分类号： H01L25/0657 , H01L21/288 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/02381 , H01L2224/05001 , H01L2224/05011 , H01L2224/05022 , H01L2224/05027 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/07811 , H01L2924/3025 , H01L2924/00
摘要： PURPOSE: To provide a semiconductor device and a method for manufacturing it, a circuit board as well as an electronic equipment capable of facilitating an electrical connection with high reliability. CONSTITUTION: This method for manufacturing a semiconductor device includes a step of forming a through hole 50 at a semiconductor chip 10 having electrodes 14, and forming a conductive layer 70 on a region including the inside of the hole 50. In this case, the hole 50 is formed larger than an opening end at an intermediate part, and the layer 70 is formed by electroless plating.
摘要翻译：目的：提供一种半导体器件及其制造方法，电路板以及能够以高可靠性促进电连接的电子设备。构成：这种制造半导体器件的方法包括在具有电极14的半导体芯片10上形成通孔50的步骤，并且在包括孔50的内部的区域上形成导电层70.在这种情况下，孔 50形成为大于中间部的开口端，层70由无电镀形成。

76. 发明公开

KR1020010053893A 반도체 소자의 패드 형성방법 失效
标题翻译：用于形成半导体器件的焊盘的方法
公开(公告)号：KR1020010053893A
公开(公告)日：2001-07-02
申请号：KR1019990054447
申请日：1999-12-02
申请人： 에스케이하이닉스 주식회사
发明人： 송기철
IPC分类号： H01L21/3213
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/05556
摘要： PURPOSE: A method for forming a pad of a semiconductor device is provided to prevent damage or peeling off of interlayer dielectric layers underneath the pad owing to an external wire bonding onto the pad. CONSTITUTION: The method includes forming metal layers(23,25) for interconnection extended under the pad(27). In the method, after an oxide layer(22) is formed on a semiconductor substrate(21), the first metal layer(23) is formed thereon and etched to form the first interconnection layer. Next, the first interlayer dielectric layer(24) is formed thereon and etched to expose a portion of the first metal layer(23). The second metal layer(25) is then formed over a resultant structure and etched to form the second interconnection layer. Next, the second interlayer dielectric layer(26) is formed on the first interlayer dielectric layer(24) and the second metal layer(25), and then etched to expose a portion of the second metal layer(25). Thereafter, a metal layer for the pad(27) is formed over a resultant structure and etched to form the pad(27). Next, a passivation layer(28) is formed thereon and etched to expose the pad(27). The first and second metal layers(23,25) under the pad(27) not only support the pad(27) but also provide electrical connection between the interconnection layers and the pad(27).
摘要翻译：目的：提供一种用于形成半导体器件的焊盘的方法，以防止由于焊盘上的外部引线接合而在焊盘下面的层间电介质层的损坏或剥离。构成：该方法包括形成用于在垫（27）下延伸的互连的金属层（23,25）。在该方法中，在半导体衬底（21）上形成氧化物层（22）之后，在其上形成第一金属层（23）并形成第一互连层。接下来，在其上形成第一层间介质层（24）并进行蚀刻以暴露第一金属层（23）的一部分。然后在所得结构上形成第二金属层（25）并进行蚀刻以形成第二互连层。接下来，在第一层间电介质层（24）和第二金属层（25）上形成第二层间电介质层（26），然后蚀刻以暴露第二金属层（25）的一部分。此后，在所得结构上形成用于焊盘（27）的金属层，并蚀刻以形成焊盘（27）。接下来，在其上形成钝化层（28）并进行蚀刻以露出焊盘（27）。衬垫（27）下面的第一和第二金属层（23,25）不仅支撑焊盘（27），而且还提供互连层和焊盘（27）之间的电连接。

77. 发明公开

KR1020010033662A 웨이퍼 패시베이션 구조 및 제조방법 有权
标题翻译：晶圆钝化结构及制造方法
公开(公告)号：KR1020010033662A
公开(公告)日：2001-04-25
申请号：KR1020007007182
申请日：1998-11-16
申请人： 인텔 코포레이션
发明人： 보어마크티
IPC分类号： H01L21/31
CPC分类号： H01L24/12 , H01L23/3135 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13006 , H01L2224/13022 , H01L2224/13099 , H01L2224/451 , H01L2224/48463 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , Y10S438/958 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： 웨이퍼패시베이션구조및 그것의제조방법이서술된다. 본발명의한 실시예에따라, 금속부재(206)로부터갭(208)에의하여공간적으로떨어진본드패드(204)를가지는금속층이기판(200) 상에형성된다. 다음으로이산화실리콘과같은제1 유전층(210)이본드패드및 금속부재상부에형성되어갭을완전히채운다. 다음으로, 제1 유전층보다큰 유전상수를가지고밀폐적인, 실리콘나이트라이드와같은제2 유전층(212)이제1 유전층상부에형성된다. 폴리이미드와같은캐핑유전층(214)는제2 유전층상에형성될수 있다. 전도성장벽층(216) 및범프(218)를포함하는제어된칩 붕괴콘택트(C-4)와같은전기콘택트(215)는모든유전층들을통하여형성되어본드패드(204)와의전기접촉을만든다.

78. 发明授权

KR100267105B1 다층패드를구비한반도체소자및그제조방법 失效
标题翻译：空值
公开(公告)号：KR100267105B1
公开(公告)日：2000-11-01
申请号：KR1019970066918
申请日：1997-12-09
申请人： 삼성전자주식회사
发明人： 김명성 , 이승록
IPC分类号： H01L21/28
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/14 , H01L2924/19041
摘要： PURPOSE: A semiconductor device having a multi-layer pad is provided to prevent crack of an interlayer dielectric caused by a probing upon a wire bonding or evaluation of an electrical characteristic by changing the pad structure of the semiconductor device having a multi-layer pad. CONSTITUTION: A semiconductor device includes the first interlayer dielectric(122) on a semiconductor substrate(120). The first conductive pad(124) is formed on the first interlayer dielectric(122) and is located in a length direction along the outer portion of one side of a pad window region(140). The second interlayer dielectric(128) is formed on the resulting surface and has the first via hole(126) through which a portion of the first conductive pad is exposed. The first conductive plug(127) is formed within the first via hole. The second conductive pad(130) electrically connected to the first conductive plug is formed on the second interlayer dielectric(128) on an upper side of the first conductive pad. The third interlayer dielectric(134) is formed on the resulting surface and has the second via hole(132) through which a portion of the second conductive pad is exposed. The second conductive plug(133) is formed within the second via hole. The third conductive pad(136) electrically connected to the second conductive plug is formed on the third interlayer dielectric and are formed to include the pad window region and its peripheral regions. A protection film(138) through which the surface of the third conductive pad in the pad window region is exposed is formed on the resulting surface.
摘要翻译：目的：提供具有多层焊盘的半导体器件，以通过改变具有多层焊盘的半导体器件的焊盘结构来防止由引线接合时的探测引起的层间电介质的裂纹或电特性的评估。构成：半导体器件包括在半导体衬底（120）上的第一层间电介质（122）。第一导电焊盘（124）形成在第一层间电介质（122）上，并且位于沿着垫窗区域（140）的一侧的外部的长度方向上。第二层间电介质（128）形成在所得表面上，并且具有第一通孔（126），第一导电焊盘的一部分通过该第一通孔露出。第一导电插塞（127）形成在第一通孔内。电连接到第一导电插塞的第二导电焊盘（130）形成在第一导电焊盘的上侧上的第二层间电介质（128）上。第三层间电介质（134）形成在所得表面上，并且具有第二通孔（132），第二导电焊盘的一部分通过该第二通孔露出。第二导电插塞（133）形成在第二通孔内。电连接到第二导电插塞的第三导电焊盘（136）形成在第三层间电介质上，并且形成为包括焊盘窗区域及其周边区域。在所得到的表面上形成保护膜（138），衬垫窗区域中的第三导电焊盘的表面露出。

79. 发明公开

KR1020000057697A 수지밀봉형 반도체장치의 제조방법 失效
标题翻译：树脂封装的半导体器件及其制造方法
公开(公告)号：KR1020000057697A
公开(公告)日：2000-09-25
申请号：KR1019997005557
申请日：1996-12-26
申请人： 가부시키가이샤 히타치세이사쿠쇼 , 가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈
发明人： 미야키요시노리 , 스즈키히로미치 , 스즈키가즈나리 , 니시타타카후미 , 이토후지오 , 쯔보사키쿠니히로 , 카메오카아키히코 , 니시쿠니히코
IPC分类号： H01L21/56
CPC分类号： H01L24/32 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/06179 , H01L2224/29007 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48647 , H01L2224/48699 , H01L2224/48747 , H01L2224/48799 , H01L2224/48847 , H01L2224/49171 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L2224/85447 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/181 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/00012
摘要： PURPOSE: A yield of the resin-encapsulated semiconductor device is provided for the semiconductor chip, bonding wires, etc., are exposed from the molded resin body. CONSTITUTION: A method for manufacturing a resin-encapsulated semiconductor device in which a die pad has an area smaller than that of a semiconductor chip mounted on the major surface of the die pad and the semiconductor chip and the die pad are encapsulated in a molded resin body. The semiconductor chip and the die pad are so arranged in the cavity of a mold that the clearance between the rear surface of the die pad and the opposed internal surface of the cavity is narrower than the clearance between the major surface of the semiconductor chip and the opposed internal surface of the cavity by the distance corresponding to the thickness of the die pad. A resin body is molded by simultaneously injecting the resin into the cavity through center gates. Thus the semiconductor chip is not moved upward by the resin injected into the space on the rear side of the chip.
摘要翻译：目的：提供半导体芯片，接合线等从模制树脂体露出树脂封装的半导体器件的产率。构成：一种制造树脂封装的半导体器件的方法，其中管芯焊盘的面积小于安装在管芯焊盘的主表面上的半导体芯片的面积，并且半导体芯片和管芯焊盘被封装在模制树脂中身体。半导体芯片和芯片焊盘被布置在模具的空腔中，芯片垫的后表面和腔的相对的内表面之间的间隙比半导体芯片的主表面和相对于腔体的内表面相应于芯片焊盘厚度的距离。通过同时将树脂注入到通过中心门的空腔中模制树脂体。因此，通过注入到芯片背面的空间中的树脂，半导体芯片不会向上移动。

80. 发明授权

KR100257912B1 수지 밀봉형 반도체 장치 失效
标题翻译：树脂密封型半导体器件
公开(公告)号：KR100257912B1
公开(公告)日：2000-06-01
申请号：KR1019960069232
申请日：1996-12-20
申请人： 닛뽕덴끼 가부시끼가이샤
发明人： 이나바다께히또
IPC分类号： H01L23/02
CPC分类号： H01L24/85 , H01L21/565 , H01L23/49503 , H01L23/49541 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/49171 , H01L2224/49173 , H01L2224/49179 , H01L2224/73265 , H01L2224/85447 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/181 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： (a) 아일랜드 영역과 복수의 내부 리드로 형성되는 리드 프레임과, 상기 내부 리드의 선단은 칩의 평면에 수직하게 봤을 때 캐비티를 형성하며, 상기 아일랜드 영역은 상기 캐비티내에 위치하며, (b) 복수의 전극을 가지며 상기 리드 프레임의 상기 아일랜드 영역상에 장착된 칩과, (c) 상기 칩의 상기 전극을 내부 리드에 연결하는 와이어를 포함하는, 수지 밀봉형 반도체 장치에 있어서, 캐비티는 칩의 각 측부와 각을 형성하는 세그먼트를 갖는 둘레를 가져, 칩의 대각선에서 코너부에 장착된 전극에 연결될 내부 리드의 선단이 상기 칩의 상기 아일랜드 영역에 가장 근접하게 배치되며, 상기 대각선에 수직한 상기 칩의 대각선 상의 일코너부에 장착된 전극 중 하나에 연결될 내부 리드의 선단이 상기 칩의 상기 아일랜드 영역으로부터 가장 멀게 배치되는 것을 특징으로 하는 수지 밀봉형 반도체 장치를 제공하는 것이다. 본 발명은, 상부 및 하부금형에 의해 형성된 공간으로 용융수지를 주입하여 반도체 장치를 밀봉하는 단계에서, 용융수지로부터 가장 큰 힘을 받는 와이어를 짧게하는 것이 가능하다. 따라서, 상기한 단계에서, 인접 와이어 사이에서 발생하는 단락을 방지하는 것이 가능하며, 이에 의해 고수율 및 고신뢰성을 갖는 수지 밀봉형 반도체 장치를 제공하는 것이다.
摘要翻译：提供了一种用树脂密封在其周围的半导体器件，包括（a）形成有岛状区域的引线框架和多个内部引线，内部引线的末端限定垂直于芯片的平面观察的空腔，岛状区域位于空腔中，（b）安装在引线框架的岛状区域上并且在其上具有多个电极的芯片，（c）用于将芯片的电极连接到内部引线的导线。空腔被限定为使得用于将内部引线连接到位于芯片的对角线D1上的拐角处的电极的电线的长度最短，并且用于连接位于垂直于对角线的对角线D2上的拐角处的电极之一的电线线D1长度最长。本发明可以在将熔融树脂引入由上下模具限定的空间并将半导体器件封装在其中的步骤中缩短从熔融树脂获得最大冲击的电线。因此，能够防止上述工序中的相邻配线之间的短路，从而提供高产率，高可靠性的树脂密封型半导体装置。

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