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61. 发明公开

KR1020050112500A 반도체 기억 장치 및 이 반도체 기억 장치의 제어 방법 有权
标题翻译：半导体存储器件，不降低其性能，即使在BURST操作期间刷新操作或字线更改操作时
公开(公告)号：KR1020050112500A
公开(公告)日：2005-11-30
申请号：KR1020040107583
申请日：2004-12-17
申请人： 후지쯔 가부시끼가이샤
发明人： 하라고타 , 야마다신이치
IPC分类号： G11C11/409
CPC分类号： G11C11/406 , G11C7/1027 , G11C7/20 , G11C11/40603 , G11C11/40615 , G11C11/4072 , G11C11/4096 , G11C7/22 , G11C11/4076
摘要： A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.

62. 发明公开

KR1020040100641A 2개의 메모리 블락 사이에 3개의 센스앰프를 가지며,인출과 기입 동작 구간이 분리되는 리프레쉬 동작을수행하는 에스램 호환 메모리 및 그 구동방법 失效
标题翻译：具有两个存储块之间的三个感测放大器的SRAM可交换存储器和执行读取和写入操作期间的刷新操作分开，以及其驱动方法
公开(公告)号：KR1020040100641A
公开(公告)日：2004-12-02
申请号：KR1020030033059
申请日：2003-05-23
申请人： (주)실리콘세븐
发明人： 김기홍 , 이선형
IPC分类号： G11C11/406
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C11/4097 , G11C2211/4065
摘要： PURPOSE: A SRAM exchangeable memory having three sense amplifiers between two memory blocks and performing a refresh operation where a read and a write operation period are separated, and its driving method are provided to improve operation speed by reducing the length of the refresh period. CONSTITUTION: Each of the first and the second memory block(110',210') include a number of DRAM cells(110a,110b,...,210a,210b,...) arranged on a matrix defined with rows and columns. Each DRAM cell has to perform a refresh operation within a refresh period to preserve stored data effectively. The DRAM cells are realized with a transmission gate gated by a word line and a capacitor storing data of a bit line transmitted through the transmission gate. Data of the DRAM cells of the first memory block is read through the first bit line pair(BLA,/BLA), and data of the DRAM cells of the second memory block is read through the second bit line pair(BLB,/BLB).
摘要翻译：目的：在两个存储器块之间具有三个读出放大器并执行读取和写入操作期间分离的刷新操作的SRAM可交换存储器，并且提供其驱动方法以通过减少刷新周期的长度来提高操作速度。构成：第一和第二存储块（110'，210'）中的每一个包括布置在由行和列定义的矩阵上的多个DRAM单元（110a，110b，...，210a，210b，...）。每个DRAM单元必须在刷新周期内执行刷新操作以有效地保存存储的数据。 DRAM单元由用字线门控的传输门和存储通过传输门传输的位线的数据的电容器来实现。通过第一位线对（BLA，/ BLA）读取第一存储块的DRAM单元的数据，通过第二位线对（BLB，/ BLB）读取第二存储块的DRAM单元的数据，。

63. 发明授权

KR100411917B1 저소비 전류에 의해 고속으로 동작하는 반도체 기억 장치 失效
标题翻译：通过电子邮件发送给朋友打印发送给朋友发送给好友
公开(公告)号：KR100411917B1
公开(公告)日：2003-12-18
申请号：KR1020010033771
申请日：2001-06-15
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 도비타요우이치
IPC分类号： G11C11/401
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40603 , G11C11/4096 , H01L21/02074 , H01L21/31055 , H01L21/31058 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.
摘要翻译：提供新的等离子体回蚀，其在铜表面的CMP工艺完成之后施加到低k电介质的表面。铜表面是互连金属的表面，互连金属嵌入在低k电介质层中。

64. 发明公开

KR1020030038318A 반도체 기억 장치 및 그 제어 방법 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：KR1020030038318A
公开(公告)日：2003-05-16
申请号：KR1020020029741
申请日：2002-05-29
申请人： 후지쯔 세미컨덕터 가부시키가이샤
发明人： 히가시호미츠히로
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G11C7/1045 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C11/4087 , G11C2211/4067
摘要： PURPOSE: To provide a semiconductor memory device in which current consumption can be reduced by providing a plurality of operation modes and performing switching control of internal signals for every operation mode with the absolute minimum control, and to provide its control method. CONSTITUTION: This device is provided with a refresh address ADD (Ref) from a refresh address counter 14 at the time of refresh mode, an address switch circuit 13 propagating one side of external addresses ADD (R/W) at the time of data input/output mode to an internal address ADD (Int), a mode discriminating circuit 11 discriminating a refresh operation request signal REQ (Ref) and a data input/output request signal REQ (R/W) and outputting a mode discriminating signal, and a switch holding circuit 12 outputting a switch switching signal SW in accordance with a mode discriminating signal M, and connection of the address switching circuit 13 is switched only at the time of change of a mode.
摘要翻译：目的：提供一种半导体存储器件，其中可以通过提供多种操作模式并且通过绝对最小控制对每个操作模式执行内部信号的切换控制来降低电流消耗，并提供其控制方法。构成：在刷新模式时，该装置具有来自刷新地址计数器14的刷新地址ADD（Ref），在数据输入时传播外部地址ADD（R / W）的一侧的地址切换电路13 /输出模式转换为内部地址ADD（Int），模式识别电路11识别刷新操作请求信号REQ（Ref）和数据输入/输出请求信号REQ（R / W）并输出模式识别信号，开关保持电路12根据模式识别信号M输出开关切换信号SW，并且地址切换电路13的连接仅在模式改变时被切换。

65. 发明公开

KR1020010020813A 반도체 메모리 장치의 동작 방법 및 반도체 메모리 장치 有权
标题翻译：用于控制半导体存储器操作和半导体存储器的方法
公开(公告)号：KR1020010020813A
公开(公告)日：2001-03-15
申请号：KR1020000024083
申请日：2000-05-04
申请人： 후지쯔 가부시끼가이샤
发明人： 스즈키다카아키 , 우치다도시야 , 사토고토쿠 , 야기시타요시마사
IPC分类号： G11C11/4063
CPC分类号： G11C11/406 , G11C5/066 , G11C11/40603 , G11C11/40611
摘要： PURPOSE: A method is provided to keep a high speed operation cycle by reducing the number of terminals required for command input and the number of terminals required for address input in a method for controlling the operation of a semiconductor memory provided with a plurality of operation modes and in a semiconductor memory provided with a plurality of operation modes. CONSTITUTION: Signals supplied from prescribed terminals are taken in as commands a plurality of times, operation modes are successively narrowed down on the basis of the commands, and an internal circuit is controlled conforming to narrowed down operation modes. As information required for decision of an operation mode are taken in a plurality of times and an operation modes are narrowed down the number of terminals required for command input is reduced. Especially when a terminal for exclusive use for command input is provided, an input pad, circuits such as an input circuit and the like are made unnecessary, and chip size is reduced.
摘要翻译：目的：提供一种用于通过减少用于控制设置有多个操作模式的半导体存储器的操作的方法中的命令输入所需的端子数量和地址输入所需的端子数来保持高速操作周期的方法并且在具有多种操作模式的半导体存储器中。构成：从规定的端子提供的信号多次作为命令，操作模式根据命令连续变窄，并且根据缩小的操作模式来控制内部电路。由于进行操作模式决定所需的信息多次，操作模式变窄，所以命令输入所需的终端数减少。特别是当提供专用于命令输入的端子时，不需要输入焊盘，诸如输入电路等的电路，并且芯片尺寸减小。

66. 发明授权

KR101881366B1 반도체 장치 및 그 동작 방법 有权
公开(公告)号：KR101881366B1
公开(公告)日：2018-07-24
申请号：KR1020120060066
申请日：2012-06-04
申请人： 에스케이하이닉스 주식회사
发明人： 문영석 , 이형동 , 권용기 , 양형균 , 김홍식
IPC分类号： G11C29/00 , G11C7/24
CPC分类号： G06F11/073 , G06F11/004 , G06F12/00 , G06F12/0804 , G06F2212/3042 , G11C7/02 , G11C7/1006 , G11C11/40603 , G11C11/4085
摘要： 본발명은워드라인디스터번스로인하여셀 데이터가손상되는것을방지할수 있는반도체장치및 그동작방법을제공하는것을목적으로한다.본발명에의한반도체장치의동작방법은제 1 기억장치에대한요청을수신하는단계;, 데이터손상위험성을나타내는정보를참고하여요청된주소에대응하는상기제 1 기억장치의제 1 워드라인에인접하는제 2 워드라인에연결된셀들의데이터손상위험성을판단하는단계, 데이터손상위험성이있는것으로판단하는경우상기제 2 워드라인에연결된셀들의데이터를제 2 기억장치에저장하는단계를포함한다.

67. 发明公开

KR20180064940A 해머 리프레쉬 동작을 수행하는 메모리 시스템 审中-公开
公开(公告)号：KR20180064940A
公开(公告)日：2018-06-15
申请号：KR20160165419
申请日：2016-12-06
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/40603 , G06F12/0246 , G11C16/3418
摘要： 메모리시스템은메모리콘트롤러및 메모리장치를포함한다. 상기메모리콘트롤러는집중적으로액세스되는해머어드레스를결정하여제공한다. 상기메모리장치는상기해머어드레스에상응하는행과물리적으로인접하는행에대한해머리프레쉬동작의타이밍을나타내는해머리프레쉬신호를내부적으로발생하고, 상기메모리콘트롤러로부터제공되는상기해머어드레스및 내부적으로발생되는상기해머리프레쉬신호에기초하여상기해머리프레쉬동작을수행한다. 해머어드레스의검출및 리프레쉬수행을메모리콘트롤러및 메모리장치에서각각수행하여해머리프레쉬동작에관한부담(burden)을분산함으로써메모리장치의사이즈를감소하고메모리시스템의전체적인성능을향상시킬수 있다.

68. 发明公开

KR1020170141290A 리프레시 동작을 수행하는 다이를 구비하는 장치 审中-实审
标题翻译：具有用于执行刷新操作的管芯的设备
公开(公告)号：KR1020170141290A
公开(公告)日：2017-12-22
申请号：KR1020177035961
申请日：2016-05-17
申请人： 마이크론 테크놀로지, 인크.
发明人： 시도,다이헤이
IPC分类号： G11C11/406 , G11C11/4076 , G11C7/22 , G11C5/06
CPC分类号： G11C11/406 , G11C7/222 , G11C11/40603 , G11C11/4076 , G11C11/4087 , G11C11/4093 , G11C5/063 , G11C7/22
摘要： 일부실시예는원래의클록신호를생성하는발진기를갖는인터페이스칩; 및제1 메모리셀들을갖는제1 메모리칩과제2 메모리셀들을갖는제2 메모리칩을포함하는장치를포함한다. 상기제1 메모리셀들은상기원래의클록신호에기초한제1 클록신호에응답하여리프레시될수 있다. 상기제2 메모리셀들은상기원래의클록신호에기초한제2 클록신호에응답하여리프레시될수 있다.
摘要翻译：一些实施例包括具有用于产生原始时钟信号的振荡器的接口芯片; 并且具有存储单元1的第一存储芯片和具有存储单元2的第二存储芯片。响应于基于原始时钟信号的第一时钟信号，可以刷新第一存储器单元。基于原始时钟信号，第二存储器单元可响应于第二时钟信号而被刷新。

69. 发明公开

KR1020170127046A 행 해머 이벤트에 응답하기 위한 방법, 장치 및 시스템 审中-实审
标题翻译：，用于响应行锤事件的装置和系统
公开(公告)号：KR1020170127046A
公开(公告)日：2017-11-20
申请号：KR1020177032329
申请日：2013-06-28
申请人： 인텔 코포레이션
发明人： 할버트,존,비. , 바인스,쿨지트,에스.
IPC分类号： G11C11/4063 , G11C11/4076
CPC分类号： G11C11/40618 , G06F3/0616 , G06F3/0659 , G06F3/0673 , G06F12/0646 , G06F12/0684 , G11C7/1072 , G11C11/40603 , G11C11/40611 , G11C11/4076
摘要： 메모리에서의행의표적화된리프레시를준비하기위해메모리장치의동작모드를용이하게하기위한기법및 메커니즘들. 실시예에서, 메모리장치는메모리컨트롤러로부터의미래명령을준비하기위한모드에있는동안하나이상의동작들을수행하는데, 이명령은적어도부분적으로한 메모리장치의제1 뱅크에서의행의표적화된리프레시를구현하기위한것이다. 그러한명령전에, 메모리장치는메모리컨트롤러로부터의또 다른명령을서비스한다. 또다른실시예에서, 다른명령을서비스하는것은메모리장치가모드에서동작하는동안, 그리고예상된미래의표적화된행 리프레시의완료전에메모리장치의제2 뱅크에메모리장치가액세스하는것을포함한다.
摘要翻译：用于促进存储器设备的操作模式以准备对存储器中的行进行有针对性刷新的技术和机制。在一个实施例中，存储器设备在处于用于从存储器控制器准备未来命令的模式中时执行一个或多个操作，该命令至少部分地实现第一存储器设备组中的行的目标刷新意。在这样的命令之前，存储器设备服务来自存储器控制器的另一个指令。在另一个实施例中，服务其他指令包括在存储器设备以模式操作并且在完成预期未来目标行刷新之前访问存储器设备到第二存储器设备组。

70. 发明授权

KR101746735B1 고신뢰성 동작을 위한 메모리 제어기를 갖는 데이터 프로세서 및 방법 有权
标题翻译：数据处理器和带有存储器控制器的方法，可靠性高
公开(公告)号：KR101746735B1
公开(公告)日：2017-06-14
申请号：KR1020167006317
申请日：2014-10-06
申请人： 어드밴스드 마이크로 디바이시즈, 인코포레이티드
发明人： 브랜들케빈엠.
IPC分类号： G06F13/16 , G11C11/406 , G06F13/12
CPC分类号： G11C11/40603 , G06F13/1605 , G06F13/1642
摘要： 데이터프로세서는메모리액세스에이전트와메모리제어기를포함한다. 메모리액세스에이전트는메모리에복수의액세스를생성한다. 메모리제어기는메모리액세스에이전트에결합되고, 메모리의특성에기초한순서로복수의메모리액세스를스케줄링한다. 메모리의특성은미리결정된시간창 내에서메모리에있는행에대한활성커맨드의허용가능한수를나타내는행 사이클페이지시간(t)을포함한다.
摘要翻译：数据处理器包括存储器访问代理和存储器控制器。内存访问代理创建多个对内存的访问。存储器控制器耦合到存储器访问代理并且基于存储器的特性以一定顺序调度多个存储器访问。存储器的特性包括行周期页面时间（t），其表示在预定时间窗口内的存储器中的行的活动命令的可允许数量。

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