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31. 发明公开

KR1020020019421A 반도체기억장치의 구동방법 无效
标题翻译：驱动半导体存储器的方法
公开(公告)号：KR1020020019421A
公开(公告)日：2002-03-12
申请号：KR1020010054348
申请日：2001-09-05
申请人： 파나소닉 주식회사
发明人： 가토요시히사 , 시마다야스히로
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/2273 , G11C11/221
摘要： PURPOSE: A method for driving a semiconductor memory is provided to improve a retention characteristic of a semiconductor memory and to stabilize operation of a read-out transistor. CONSTITUTION: A method for driving a semiconductor memory provided with a plurality of memory cells consisting of ferroelectric capacitors(CF11,CF12,CF13,CF14) and cell selecting transistors(Q11,Q12,Q13,Q14) being connected in series includes the steps of: connecting the capacitive load by inserting the other side electrode of the data read-out ferroelectric capacitor into the second common node, applying the read-out voltage to a set line, removing the read-out voltage applied to the set line and setting the read-out voltage applied to the set line to the size of polarization displacement of the read-out ferroelectric capacitor before reading out data when the read-voltage is eliminated during the removing step.
摘要翻译：目的：提供一种用于驱动半导体存储器的方法，以改善半导体存储器的保持特性并稳定读出晶体管的工作。构成：串联连接的由铁电电容器（CF11，CF12，CF13，CF14）和电池选择用晶体管（Q11，Q12，Q13，Q14）构成的多个存储单元的半导体存储器的驱动方法，：通过将数据读出铁电电容器的另一侧电极插入第二公共节点来连接电容性负载，将读出电压施加到设定线，去除施加到设定线的读出电压，在去除步骤期间消除读取电压时读出数据之前，将读出的电压施加到读出的铁电电容器的极化位移的大小的读出电压。

32. 发明公开

KR1020010076884A 불휘발성 강유전체 메모리 장치 및 그에 따른 구동방법 失效
标题翻译：非易失性电介质存储器件及其驱动方法
公开(公告)号：KR1020010076884A
公开(公告)日：2001-08-17
申请号：KR1020000004303
申请日：2000-01-28
申请人： 에스케이하이닉스 주식회사
发明人： 강희복
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/221 , G11C5/063 , G11C7/06 , G11C7/12 , G11C11/2257 , G11C11/2273
摘要： PURPOSE: A non-volatile ferroelectric memory device and a driving method thereof are to minimize chip cycle time to improve chip characteristic, and also prevent loading difference of a bit line due to capacitance difference between a main cell and a reference cell. CONSTITUTION: A plurality of sub cell arrays is comprised of a plurality of main cells and at least one reference cell. The first transistor has a gate connected to a reference word line and a drain connected to a bit line. The second transistor is controlled by a reference bit line equalizing signal applied to a gate, and has a drain connected to a source of the first transistor and a source connected to a ground voltage terminal. A plurality of ferroelectric capacitors are comprised of the first terminal, the second terminal and a ferroelectric layer formed between the first and second terminals. The first terminal is connected to the source of the first transistor. The second terminal is connected to a reference plate line.
摘要翻译：目的：非易失性铁电存储器件及其驱动方法是使芯片周期时间最小化以提高芯片特性，并且还防止由于主单元和参考单元之间的电容差引起的位线的负载差异。构成：多个子单元阵列由多个主单元和至少一个参考单元构成。第一晶体管具有连接到参考字线的栅极和连接到位线的漏极。第二晶体管由施加到栅极的参考位线均衡信号控制，并且具有连接到第一晶体管的源极的漏极和连接到接地电压端子的源极。多个铁电电容器由第一端子，第二端子和形成在第一端子和第二端子之间的铁电层构成。第一端子连接到第一晶体管的源极。第二端子连接到参考板线。

33. 发明公开

KR1020010004229A 셀 저장노드의 전압다운 보상을 위한 저항을 갖는 강유전체 메모리 장치의 메모리 셀 失效
标题翻译：具有高电压的电解存储器件，用于补偿电池电压降低
公开(公告)号：KR1020010004229A
公开(公告)日：2001-01-15
申请号：KR1019990024851
申请日：1999-06-28
申请人： 에스케이하이닉스 주식회사
发明人： 박제훈
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C5/063 , G11C11/2297
摘要： PURPOSE: A ferroelectric memory device is provided to reduce a power consumption by preventing a charge from reducing due to a leakage current of on a memory cell storage node. CONSTITUTION: A ferroelectric memory device has a cell using a ferroelectric capacitor as a storage. The cell includes the ferroelectric capacitor(301), a switching transistor(311) and a high resistance unit(321). The ferroelectric capacitor has a first electric terminal receiving a fixed first voltage level from a first voltage supply terminal and a second electric terminal connected with a storage node. The switching transistor inputs an on/off control signal on its own gate. The source-drain path of the switching transistor connects with the storage node and a signal line. The high resistance unit is connected between the first voltage supply terminal and the storage node for compensating a voltage down of the storage node. The high resistance unit has a resistance value of 500-700 kiloohm.
摘要翻译：目的：提供一种强电介质存储器件，用于通过防止由于存储单元存储节点上的漏电流导致的电荷减少而降低功耗。构成：铁电存储器件具有使用铁电电容器作为存储器的单元。电池包括铁电电容器（301），开关晶体管（311）和高电阻单元（321）。铁电电容器具有从第一电压供给端子和与存储节点连接的第二电气端子接收固定的第一电压电平的第一电气端子。开关晶体管在其门上输入开/关控制信号。开关晶体管的源极 - 漏极路径与存储节点和信号线连接。高电阻单元连接在第一电压供给端子和存储节点之间，用于补偿存储节点的电压降。高电阻单元的电阻值为500-700千欧。

34. 发明公开

KR1020000043969A 비휘발성 강유전체 메모리장치 失效
标题翻译：非挥发性框架
公开(公告)号：KR1020000043969A
公开(公告)日：2000-07-15
申请号：KR1019980060408
申请日：1998-12-29
申请人： 현대반도체 주식회사
发明人： 강희복
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/2273 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/14 , G11C11/221 , G11C11/2257
摘要： PURPOSE: A non-volatile FRAM(ferroelectric random access memory) is provided to improve an operating characteristic and to lengthen a life by uniformly maintaining a bit line inducing voltage by a reference cell and a bit line inducing voltage by a main cell with equalizing an accessed number of the main cell and the reference cell. CONSTITUTION: A voltage of node N3 is used as a gate input of a fourth NMOS transistor(MN4). A voltage of output terminal is used as the gate input of a fifth NMOS transistor(MN5). If the voltage of node N3 is larger than the voltage of output terminal, a voltage of node N4 is lessened and a voltage of N5 is enlarged. The lessened voltage of node N4 enlarges an on resistance of ninth NMOS transistor(MN9) by feeding back to the ninth NMOS transistor(MN9). A level of the output terminal is raised by decreasing an amount of current discharged to the output terminal. If the voltage of node N3 is smaller than the voltage of output terminal, the voltage of node N5 is lessened and the voltage of node N4 is enlarged. The enlarged voltage of node N4 lessens the on resistance of the ninth NMOS transistor(MN9) by feeding back to the ninth NMOS transistor(MN9). The level of the output terminal is decreased by increasing the amount of current discharged to the output terminal.
摘要翻译：目的：提供非易失性FRAM（铁电随机存取存储器），以通过均衡地维持基准单元的位线感应电压和主电池的位线感应电压来均衡维持工作特性并延长使用寿命访问的主单元和参考单元的编号。构成：节点N3的电压用作第四NMOS晶体管（MN4）的栅极输入。输出端子的电压用作第五NMOS晶体管（MN5）的栅极输入。如果节点N3的电压大于输出端子的电压，节点N4的电压减小，N5的电压变大。节点N4的降低的电压通过反馈到第九NMOS晶体管（MN9）而放大第九NMOS晶体管（MN9）的导通电阻。输出端子的电平通过减少向输出端子放电的电流量而上升。如果节点N3的电压小于输出端的电压，则节点N5的电压减小，节点N4的电压增大。节点N4的放大电压通过反馈到第九NMOS晶体管（MN9）来减小第九NMOS晶体管（MN9）的导通电阻。通过增加放电到输出端子的电流量来减小输出端子的电平。

35. 发明公开

KR1020000042467A 강유전체 메모리 소자 无效
标题翻译：电磁存储器件
公开(公告)号：KR1020000042467A
公开(公告)日：2000-07-15
申请号：KR1019980058634
申请日：1998-12-24
申请人： 에스케이하이닉스 주식회사
发明人： 계훈우 , 류지환
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C5/063 , G11C7/06 , G11C11/221
摘要： PURPOSE: A ferroelectric memory device is provided to reduce a size of an amplifier and to improve an operating speed by re-storing amplified and read data with a sense amplifier separated an input terminal and an output terminal. CONSTITUTION: A voltage exposed into a plate line(PL) is transferred to a sense amplifier and is controlled by a selected column address. In reading a value stored in an XO, the voltage exposed into a pI0 is transferred to the sense amplifier by selecting a wI0 and being a psI0 to 'high'. A reference voltage of the sense amplifier is to be Vcc/2-(V1-V2)/2. An output of the sense amplifier is sent to an output path and fed back to a bit line for re-storing read data after amplifying the detection.
摘要翻译：目的：提供强电介质存储器件以减小放大器的尺寸并通过利用分离了输入端子和输出端子的读出放大器重新存储放大和读取数据来提高操作速度。构成：暴露于板线（PL）的电压被传送到读出放大器，并由选定的列地址控制。在读取存储在XO中的值时，暴露于pI0中的电压通过选择wI0并作为psI0至“高”来传送到读出放大器。读出放大器的参考电压为Vcc / 2-（V1-V2）/ 2。读出放大器的输出被发送到输出路径并反馈到位线，以便在放大检测之后重新存储读取数据。

36. 发明公开

KR20180037068A 강유전성 메모리 셀들을 동작시키는 방법들, 및 관련된 강유전성 메모리 셀들 有权
标题翻译：操作铁电存储器单元的方法以及操作铁电存储器单元的方法
公开(公告)号：KR20180037068A
公开(公告)日：2018-04-10
申请号：KR20187009019
申请日：2016-08-18
申请人： 마이크론 테크놀로지, 인크
发明人： 니콜레스,스티븐씨. , 샤반,아쇼니타에이. , 록클라인,매튜엔.
IPC分类号： G11C11/22 , H01L27/11502
CPC分类号： G11C11/225 , G11C11/22 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C11/5657 , G11C13/047 , G11C14/00 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/75
摘要： 강유전성메모리셀을동작시키는방법들. 방법은강유전성메모리셀에양의바이어스전압및 음의바이어스전압중 하나를인가하는단계를포함하며, 상기강유전성메모리셀은상부전극, 하부전극, 상부전극및 하부전극사이에서의강유전성재료, 및강유전성재료및 상부전극및 하부전극중 하나사이에서의계면재료를포함한커패시터를포함한다. 방법은강유전성메모리셀의분극을스위칭하기위해양의바이어스전압및 음의바이어스전압중 또다른하나를강유전성메모리셀에인가하는단계를포함하며, 여기에서음의바이어스전압의절대값은양의바이어스전압의절대값과상이하다. 강유전성메모리셀들이또한설명된다.
摘要翻译：操作铁电存储器单元的方法。方法包括施加正偏压电压的偏压电压中的一个和一个铁电存储单元，其中，所述铁电存储单元是上部电极，下部电极，上部电极和下部电极之间的铁电材料eseoui的负极，和与强电介质材料的步骤以及在上电极和下电极中的一个之间包括界面材料的电容器。方法中的负偏压的绝对值和正偏置电压的偏置电压的进一步的一个和负切换铁电存储器单元，其包括的偏振：将铁电存储器单元，所述偏置电压，其中所述量。“ 还描述了铁电存储器单元。

37. 发明授权

KR101679490B1 집적 회로 구성요소들, 스위치들, 및 메모리 셀들 有权
标题翻译：集成电路组件开关和存储器单元
公开(公告)号：KR101679490B1
公开(公告)日：2016-11-24
申请号：KR1020147024898
申请日：2013-01-23
申请人： 마이크론 테크놀로지, 인크
发明人： 샌더,거티,에스.
IPC分类号： H01L27/24 , H01L27/115 , H01L29/82 , C01B31/04
CPC分类号： H01L27/1159 , B82Y10/00 , G11C11/221 , H01L27/11521 , H01L29/1606 , H01L29/513 , H01L29/516 , H01L29/7788 , H01L29/78391
摘要： 스위치는한 쌍의전극들사이에서세로방향으로연장되며상기쌍의양쪽전극들에도전성으로연결되는그래핀구조를포함한다. 제 1 및제 2 전기적도전성구조들은그래핀구조의측면바깥쪽으로및 서로로부터그래핀구조의대향측면들상에있다. 강유전성재료는측면으로그래핀구조및 제 1 및제 2 전기적도전성구조들중 적어도하나사이에있다. 제 1 및제 2 전기적도전성구조들은그래핀구조및 강유전성재료를가로지르는전기장의인가에의해“온”및 “오프”상태들로스위치를제공하도록구성된다. 스위치들이아닐수 있는집적회로의구성요소들을포함한, 다른실시예들이개시된다.
摘要翻译：开关包括在一对电极之间纵向延伸并且导电地连接到所述对的两个电极的石墨烯结构。第一和第二导电结构在石墨烯结构的横向外侧并且彼此在石墨烯结构的相对侧上。铁电材料横向在石墨烯结构和第一和第二导电结构中的至少一个之间。第一和第二导电结构被配置为通过在整个石墨烯结构和铁电材料上施加电场来将开关提供到“导通”和“关闭”状态。公开了其他实施例，包括可以不是开关的集成电路的部件。

38. 发明公开

KR1020160072264A 멀티-비트 강유전체 메모리 디바이스 및 멀티-비트 강유전체 메모리 디바이스를 형성하는 방법 有权
标题翻译：多位电磁存储器件及其形成方法
公开(公告)号：KR1020160072264A
公开(公告)日：2016-06-22
申请号：KR1020167014410
申请日：2014-10-29
申请人： 마이크론 테크놀로지, 인크.
发明人： 카르다,카말엠. , 기얼리,에프.다니엘 , 라마스와미,디.브이.널말 , 모우리,샨드라브이.
IPC分类号： H01L43/12 , H01L43/02 , H01L43/10 , G11C11/22 , G11C11/56 , H01L27/115 , H01L49/02
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L28/40 , H01L43/02 , H01L43/12 , H01L43/10
摘要： 멀티-비트강유전체메모리디바이스및 멀티-비트강유전체메모리디바이스를형성하는방법이제공된다. 멀티-비트강유전체메모리디바이스를형성하는일례의방법은비아의제1 측면상에제1 강유전체재료를형성하는단계, 비아의제2 측면을노출시키도록재료를제거하는단계, 및비아의제1 측면에비해다른두께로비아의제2 측면상에제2 강유전체재료를형성하는단계를포함할수 있다.

39. 发明公开

KR1020150029015A 전력 중단의 기간에 걸쳐 로직 기능들을 구현하는 내장형 비휘발성 메모리 회로 审中-实审
标题翻译：用于在断电期间实施逻辑功能的嵌入式非易失性存储器电路
公开(公告)号：KR1020150029015A
公开(公告)日：2015-03-17
申请号：KR1020157003022
申请日：2013-07-01
申请人： 래디언트 테크놀러지즈, 인코포레이티드
发明人： 에반스,조셉티.
IPC分类号： G11C5/14 , G11C16/30 , H01L27/115 , H03K19/17
CPC分类号： G11C5/148 , G11C7/1006 , G11C7/20 , G11C7/24 , G11C8/20 , G11C11/221 , G11C14/00 , G11C16/22 , G11C19/005 , H01L27/11502 , H03K3/356008 , G11C16/30 , H03K19/17
摘要： AML(자율적 강유전체 메모리 래치)를 갖는 회로가 개시된다. AML 입력, AML 출력, 제1 AML 전력 접촉, 제2 AML 전력 접촉 및 AML 상태에 의해 특성화되는 AML, 및 AML 입력 또는 AML 출력 중 하나와 직렬인 제1 스위치를 포함한다. 스위치는 전력이 제1 AML 전력 접촉과 제2 AML 전력 접촉 사이에 제공될 때, AML의 상태가 변경되는 것을 방지하도록 위치된다. 본 발명의 하나의 양태에서, 회로는 AML 입력 또는 AML 출력 중 다른 하나와 직렬인 제2 스위치 및 AML 입력 또는 AML 출력과 직렬인 래치를 포함할 수 있다. 래치는 직접적 경로가 AML 출력과 AML 입력 사이에 다시 존재하지 않도록 위치된다.

40. 发明公开

KR1020140040010A 강유전체 메모리 기록 및 비-파괴적 판독 시스템 및 방법 审中-实审
标题翻译：用于书写和非解密阅读电磁记忆的系统和方法
公开(公告)号：KR1020140040010A
公开(公告)日：2014-04-02
申请号：KR1020130110990
申请日：2013-09-16
申请人： 팔로 알토 리서치 센터 인코포레이티드
发明人： 데이비드에릭슈와르츠
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/223
摘要： Ferroelectric memory cell configurations, a system for controlling writing and reading to those configurations, and a method for employing those configurations for writing and reading ferroelectric memories are provided. The ferroelectric memory cells according to the disclosed configurations are read without disturbing the stored data, i.e., not requiring any modification of the stored polarization state of the ferroelectric memory cell to read the stored data, thus providing a ″non-destructive″ reading process. The ferroelectric memory cells are read without required that a charge or a sense amplifier be a part of the ferroelectric memory cell. Various transistor configurations provide a capability to read a signal effect through a transistor channel as an indication of capacitance of a ferroelectric memory cell polarization state.
摘要翻译：提供铁电存储单元配置，用于控制对这些配置的写入和读取的系统以及采用这些配置来写入和读取铁电存储器的方法。读取根据所公开的配置的铁电存储单元，而不干扰所存储的数据，即不需要对存储的强电介质存储单元的存储的偏振状态进行任何修改以读取存储的数据，从而提供“非破坏性”读取过程。读取铁电存储单元，而不需要电荷或读出放大器作为铁电存储单元的一部分。各种晶体管配置提供通过晶体管沟道读取信号效应作为铁电存储器单元极化状态的电容的指示的能力。

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