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21. 发明公开

KR1020160148719A 멀티레벨 작동을 하는 비휘발성 광전지 메모리 셀 无效
标题翻译：具有多次操作的非挥发性电磁记忆体
公开(公告)号：KR1020160148719A
公开(公告)日：2016-12-26
申请号：KR1020167034979
申请日：2015-06-03
申请人： 사빅 글로벌 테크놀러지스 비.브이.
发明人： 박,지,훈 , 알샤리프,후삼,엔. , 칸,모드.에이 , 오데,이햅,엔.
IPC分类号： G11C11/22 , G11C11/56 , H01L43/08
CPC分类号： G11C11/2275 , G11C11/221 , G11C11/2273 , G11C11/2277 , G11C11/5657 , H01L27/11509 , H01L27/20 , H01L43/08
摘要： 상술한강유전체전계효과트랜지스터 (ferroelectric field effect transistor, FeFET), 강유전체컨덴서및 강유전체다이오드와같은강유전체성분은본 발명에에서설명한바와같이멀티-레벨메모리셀로서작동될수있다. 각각의멀티-레벨메모리셀에다중비트의정보를저장하는것은강유전체메모리셀들로구성된강유전체성분들의어레이에결합된컨트롤러에의해수행될수 있다. 컨트롤러는강유전체층을포함하는멀티-레벨메모리셀에기록하기위한비트패턴을수신하는단계; 상기수신된비트패턴의적어도일부분에기초하여상기메모리셀에기록펄스를인가하기위한펄스지속시간을선택하는단계;및상기선택된펄스시간을갖는메모리셀에적어도하나의기록펄스를인가하는단계, 이때 상기적어도하나의기록펄스는상기수신된비트패턴을나타내는상기강유전체층 내에잔류분극을생성하는, 단계를포함하여실행한다.
摘要翻译：诸如铁电场效应晶体管（FeFET），铁电电容器和铁电二极管的铁电元件可以作为如本发明所述的多电平存储器单元来操作。在每个多级存储器单元中存储多个位的信息可以由耦合到被配置为铁电存储单元的铁电元件阵列的控制器来执行。控制器可以执行以下步骤：接收用于写入到包括铁电层的多层存储单元的位模式; 至少部分地基于所接收的位模式，选择用于将写入脉冲施加到存储器单元的脉冲持续时间; 以及向具有所选择的脉冲持续时间的存储单元施加至少一个写入脉冲，其中所述至少一个写入脉冲在所述铁电层内产生代表所接收的位模式的剩余极化。

22. 发明公开

KR1020150144818A 강유전체 전계 효과 트랜지스터 메모리 어레이를 갖는 장치 및 관련된 방법 有权
标题翻译：具有电磁场效应晶体管存储器阵列的装置及相关方法
公开(公告)号：KR1020150144818A
公开(公告)日：2015-12-28
申请号：KR1020157034914
申请日：2014-05-15
申请人： 마이크론 테크놀로지, 인크
发明人： 라마스와미,디.브이.니르말 , 존슨,아담디.
IPC分类号： G11C11/22
CPC分类号： H01L27/11597 , G11C11/22 , G11C11/221 , G11C11/223 , G11C11/2255 , G11C11/2257 , H01L29/78391
摘要： 장치는 3차원메모리어레이아키텍처내에수평으로및 수직으로적층된전계효과트랜지스터 (FET) 구조들, 수직으로연장되고및 수평으로간격을두고 between 상기복수개의 FET 구조들사이에서수평으로간격된게이트들, 및 FET 구조들및 게이트들을분리하는강유전체재료를포함한다. 개별강유전체 FET들 (FeFET들)은 FET 구조들, 게이트들, 및강유전체재료의인터섹션들에형성된다. 다른장치는복수개의비트라인들및 워드라인들을포함한다. 각각의비트라인은강유전체재료와결합된적어도두개의측면들을가져서각각의비트라인은복수개의 FeFET들을형성하도록인접한게이트들에의해공유된다. 메모리어레이를동작시키는방법은복수개의 FeFET 메모리셀들에대하여희망하는동작을위해복수개의워드라인들및 디지트라인들에전압들의조합을인가하는단계를포함하되, 적어도하나의디지트라인은인접한게이트들에의해액세스가능한복수개의 FeFET 메모리셀들을가진다.
摘要翻译：一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。另一种装置包括多个位线和字线。每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻栅极共享以形成多个FeFET。操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。

23. 发明公开

KR1020150129801A 개선된 피로 및 항복 특성을 동반하는 강유전성 축전기 审中-实审
标题翻译：具有改进的疲劳和断裂特性的电磁电容器
公开(公告)号：KR1020150129801A
公开(公告)日：2015-11-20
申请号：KR1020157028270
申请日：2014-03-06
申请人： 사우디 베이식 인더스트리즈 코포레이션
发明人： 칸,모흐드,에이. , 알사리프,후삼,엔. , 오데,이합,엔. , 알마드호운,마흐무드,엔.
IPC分类号： H01L49/02 , H01L51/00 , H01L51/05 , G11C11/22
CPC分类号： G11C11/22 , G11C11/221 , H01L28/55 , H01L51/004 , H01L51/0043 , H01L51/0591 , Y10T428/24802
摘要： 본발명은강유전성재료(12) 및축전기에서이를사용하는방법을개시한다. 강유전성재료(12)는강유전성중합체(12a) 및저유전율을나타내는유전성중합체(12b)의중합체블렌드를포함한다. 유전성중합체(12b)는복수의분리된영역들(12b)이강유전성중합체(12a) 내부에형성되도록강유전성중합체(12a)로부터상분리될수 있다. 강유전성재료(12)는 2개의전극 (11) 및 (13) 사이에배치된다. 복수의영역들(12b)은전하를저장하기위한전하-포획영역으로작용하며전하캐리어가강유전성중합체(12a) 전체에걸쳐자유롭게이동하는것을방지한다.

24. 发明公开

KR1020130024486A 강유전체 메모리 소자 및 그의 제조 방법 有权
标题翻译：电磁存储器件及其制备方法
公开(公告)号：KR1020130024486A
公开(公告)日：2013-03-08
申请号：KR1020110087959
申请日：2011-08-31
申请人： 서울대학교산학협력단
发明人： 노태원 , 이대수 , 윤종걸
IPC分类号： H01L27/105
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2275 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L27/228 , H01L28/55
摘要： PURPOSE: A ferroelectric memory device and a method for fabricating the same are provided to secure high capacity by controlling multilevel polarization. CONSTITUTION: A transistor is electrically connected to a ferroelectric capacitor(130). A current limiter(150) includes a transistor. The ferroelectric capacitor performs a polarization switching process. The ferroelectric capacitor includes multilevel polarization. The multilevel polarization is generated in the ferroelectric capacitor by controlling displacement current.
摘要翻译：目的：提供铁电存储器件及其制造方法，以通过控制多电平极化来确保高容量。构成：晶体管电连接到铁电电容器（130）。限流器（150）包括晶体管。铁电电容器进行极化切换处理。铁电电容器包括多电平极化。通过控制位移电流在铁电电容器中产生多电平极化。

25. 发明公开

KR1020120124226A 메모리 소자 및 그 제조 방법 无效
标题翻译：存储器件及其制造方法相同
公开(公告)号：KR1020120124226A
公开(公告)日：2012-11-13
申请号：KR1020110041993
申请日：2011-05-03
申请人： 삼성전자주식회사
发明人： 김선국 , 최웅 , 한승훈 , 진용완 , 이상윤
IPC分类号： H01L27/105 , H01L21/8229
CPC分类号： B82Y10/00 , B82Y40/00 , G11C11/221 , H01L21/31144 , H01L27/10 , H01L27/101 , H01L27/11507 , H01L27/222 , H01L28/55
摘要： PURPOSE: A memory device and a manufacturing method thereof are provided to improve information retention characteristics by forming a plurality of recording layers of nanometer size in order to not be each other influenced. CONSTITUTION: A bottom electrode(11) is formed on a substrate(10). A plurality of information storage units(12) is formed on the bottom electrode. The plurality of information storage units comprises a plurality of information storage layers(12a,12b). The plurality of information storage units is mutually separated. The plurality of information storage units is comprised of ferroelectric material, ferromagnetic material, or anti-ferromagnetic material. An insulating layer is formed on the bottom electrode and the plurality of information storage units. The insulating layer is comprised of a low-k dielectric in which dielectric constant is lower than SiO2.
摘要翻译：目的：提供存储器件及其制造方法，以通过形成多个纳米尺寸的记录层来改善信息保持特性，从而不受其他影响。构成：在基板（10）上形成底部电极（11）。多个信息存储单元（12）形成在底部电极上。多个信息存储单元包括多个信息存储层（12a，12b）。多个信息存储单元相互分离。多个信息存储单元由铁电材料，铁磁材料或反铁磁材料构成。绝缘层形成在底部电极和多个信息存储单元上。绝缘层由介电常数低于SiO 2的低k电介质构成。

26. 发明公开

KR1020070077460A 메모리 失效
标题翻译：记忆
公开(公告)号：KR1020070077460A
公开(公告)日：2007-07-26
申请号：KR1020070006543
申请日：2007-01-22
申请人： 산요덴키가부시키가이샤
发明人： 미야모또히데아끼
IPC分类号： G11C11/22 , G11C11/401 , G11C11/406
CPC分类号： G11C11/22 , G11C2029/5002 , G11C11/225 , G11C11/221 , G11C11/2273 , G11C11/2275
摘要： A memory is provided to suppress the increase of circuit size while preventing the generation of imprint, and to prevent the reduction of access demand time and the increase of power consumption. A plurality of memory cell blocks includes a plurality of memory cells. A refresh control unit performs a read operation and a rewrite operation on the memory cell. A first frequency detection unit detects access frequency to the memory cell. A second frequency detection unit detects access frequency every memory cell block. A third frequency detection unit detects the frequency when the sum of the access frequency every memory cell block counted by the second frequency detection unit does not reach a fixed frequency, when the sum of the access frequency to the memory cell has reached a fixed frequency by the first frequency detection unit.
摘要翻译：提供存储器以抑制电路尺寸的增加，同时防止产生印记，并且防止访问需求时间的减少和功耗的增加。多个存储单元块包括多个存储单元。刷新控制单元对存储单元执行读取操作和重写操作。第一频率检测单元检测存储单元的存取频率。第二频率检测单元检测每个存储单元块的存取频率。第三频率检测单元，当存储单元的访问频率之和达到固定频率时，当第二频率检测单元计数的每个存储单元块的存取频率之和未达到固定频率时，检测频率第一频率检测单元。

27. 发明公开

KR1020070005445A 강유전체 기억 장치 有权
标题翻译：电力储存装置
公开(公告)号：KR1020070005445A
公开(公告)日：2007-01-10
申请号：KR1020050109604
申请日：2005-11-16
申请人： 후지쯔 가부시끼가이샤
发明人： 요시오카히로시
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/2273 , G11C5/063 , G11C5/14 , G11C7/12 , G11C7/22 , G11C11/221 , G11C11/2297
摘要： A ferroelectric memory device is provided to have good read operation characteristics regardless of the capacitance of a bit line, by comprising a timing control circuit for controlling detection timing of data on the bit line. A ferroelectric capacitor maintains data by polarization. A bit line inputs/outputs data on the ferroelectric capacitor. A first switching device selectively connects the ferroelectric capacitance and the bit line. A first transistor is connected to the bit line and a reference potential. A reference ferroelectric capacitor(CR1) maintains fixed data. A reference bit line(Lref) inputs/outputs data on the reference ferroelectric capacitor. A reference switching device(105) selectively connects the reference ferroelectric capacitor and the reference bit line. A second transistor is connected to the reference bit line and the reference potential. A potential control circuit controls the potential of the bit line when the bit line is connected to the ferroelectric capacitor, and controls the potential of the reference bit line when the reference bit line is connected to the reference ferroelectric capacitor. A timing control circuit controls detection timing of the data of the bit line.
摘要翻译：通过包括用于控制位线上的数据的检测定时的定时控制电路，提供强电介质存储器件以具有良好的读取操作特性，而不管位线的电容如何。铁电电容器通过极化保持数据。位线输入/输出铁电电容上的数据。第一开关器件选择性地连接铁电电容和位线。第一晶体管连接到位线和参考电位。参考铁电电容器（CR1）保持固定数据。参考位线（Lref）输入/输出参考铁电电容器上的数据。参考开关装置（105）选择性地连接参考铁电电容器和参考位线。第二晶体管连接到参考位线和参考电位。当位线连接到铁电电容器时，电位控制电路控制位线的电位，并且当参考位线连接到参考铁电电容器时控制参考位线的电位。定时控制电路控制位线的数据的检测定时。

28. 发明公开

KR1020060080850A 반도체 메모리 有权
标题翻译：半导体内存
公开(公告)号：KR1020060080850A
公开(公告)日：2006-07-11
申请号：KR1020050051336
申请日：2005-06-15
申请人： 후지쯔 가부시끼가이샤
发明人： 후쿠시이사오 , 가와시마쇼이치로
IPC分类号： G11C11/22
CPC分类号： H01L27/11507 , G11C11/22 , H01L27/11502 , G11C11/221 , G11C7/18 , G11C8/14 , G11C11/2273
摘要： A ferroelectric memory has a plurality of memory cells respectively having a cell transistor and ferroelectric capacitor whose one terminal is connected with the cell transistor, a plurality of word lines respectively connected with said cell transistor, a plurality of plate lines connected with the other terminal of said ferroelectric capacitor and intersecting with said word lines, a plurality of local bit lines connected with said cell transistors, and a global bit line that is selectively connected with local bit lines. Furthermore, the ferroelectric memory has a sensing amplifier unit that detects the amount of charging of the local bit lines from said memory cells while maintaining the potential of the local bit lines at a potential equivalent to the non-selected plate lines, during reading.
摘要翻译：本发明提供了一种减小了存储单元的占用面积的铁电存储器。

29. 发明公开

KR1020060051587A 메모리 有权
标题翻译：记忆
公开(公告)号：KR1020060051587A
公开(公告)日：2006-05-19
申请号：KR1020050088738
申请日：2005-09-23
申请人： 산요덴키가부시키가이샤
发明人： 사까이나오후미
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/2273 , G11C5/14 , G11C7/1069 , G11C7/18 , G11C8/14 , G11C11/221 , G11C11/2297
摘要： A memory capable of easily setting a reference potential and correctly determining data is provided. This memory comprises a ferroelectric capacitor holding data, and a driving line and a data line linked with the ferroelectric capacitor. The memory applies a voltage pulse to the ferroelectric capacitor through the driving line when reading the data thereby generating a negative potential on the data line if the ferroelectric capacitor holds first data, or generating a positive potential on the data line if the ferroelectric capacitor holds second data.
摘要翻译：可以很容易地设置参考电位并提供能够准确识别数据的存储器。该存储器具有用于保持数据的铁电电容器以及连接到铁电电容器的驱动线和数据线。并且，在数据读出时，通过所述驱动线向强电介质电容器中，当铁电电容器保持第一数据，并在数据线中产生负电势施加电压脉冲，维持第二数据铁电电容器，数据线中会产生正电位。

30. 发明公开

KR1020060043532A 반도체 메모리 有权
标题翻译：半导体内存
公开(公告)号：KR1020060043532A
公开(公告)日：2006-05-15
申请号：KR1020050019257
申请日：2005-03-08
申请人： 후지쯔 가부시끼가이샤
发明人： 후쿠시이사오 , 모리타게이조 , 가와시마쇼이치로
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/04 , G11C7/06 , G11C7/12 , G11C11/4094 , G11C11/2273 , G11C5/143 , G11C7/1069 , G11C11/221
摘要： A controller controls charge transferability of charge transferring circuit to transfer charge read out from a storage circuit, based on change in bit line voltage. A leakage controller reduces charge transfer between storage circuit and bit line, before reading data from the cell. The storage circuit generates read voltage for read circuit, based on logical value of the stored data.
摘要翻译：本发明涉及通过电荷转移电路的电荷积累电路。控制电路根据从存储单元读出的电荷的位线电压的变化来控制电荷传输电路的电荷传输能力。在位线上读出电荷之前，泄漏控制电路在读取操作中暂时降低电荷传输电路的电荷传输能力。在通过泄漏控制电路从存储单元读出数据之前，可以防止位线和电荷存储电路之间的电荷传输。因此，电荷累积电路产生读取电压，使得读取电路根据在存储器单元中累积的数据的逻辑值充分操作。

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