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11. 发明公开

KR1020130021063A 초광대역 레이더 有权
标题翻译：超声波雷达
公开(公告)号：KR1020130021063A
公开(公告)日：2013-03-05
申请号：KR1020110083352
申请日：2011-08-22
申请人： 연세대학교 산학협력단
发明人： 김태욱
IPC分类号： G01S13/06
CPC分类号： G01S7/285 , G01S7/412 , G01S13/0209 , G01S13/04 , G01S13/886 , H03M1/1245
摘要： PURPOSE: An ultra-wideband radar is provided to improve accuracy of determination on a measurement target. CONSTITUTION: An ultra-wideband radar(100) includes a transmission unit(110), a reception unit(120), and a determination unit(130). The transmission unit outputs a signal to a measurement target. The reception unit receives a reflection signal corresponding to the output signal. The determination unit determines the measurement target by receiving the reflection signal from the reception unit. The determination unit directly simples the reflection signal and determines the measurement target by comparing the directly sampled signal or the directly sampled signal and the stored reflection signal. [Reference numerals] (110) Transmission unit; (120) Reception unit; (130) Determination unit; (AA) Object
摘要翻译：目的：提供超宽带雷达，以提高测量目标的确定精度。构成：超宽带雷达（100）包括传输单元（110），接收单元（120）和确定单元（130）。发送单元向测量对象输出信号。接收单元接收与输出信号对应的反射信号。确定单元通过接收来自接收单元的反射信号来确定测量目标。确定单元直接模拟反射信号，并通过比较直接采样信号或直接采样信号与存储的反射信号来确定测量目标。（附图标记）（110）传输单元; （120）接待单位; （130）确定单位; （AA）对象

12. 发明授权

KR101014771B1 고속 신호 처리 장치 및 방법 有权
标题翻译：装置和处理高速信号的方法
公开(公告)号：KR101014771B1
公开(公告)日：2011-02-14
申请号：KR1020100016588
申请日：2010-02-24
申请人： 엘아이지넥스원 주식회사
发明人： 신규식 , 이왕용
IPC分类号： H03M1/12
CPC分类号： H04L27/0002 , G11C27/02 , H03M1/12 , H03M1/1245 , H03M2201/196
摘要： PURPOSE: An apparatus and a method for processing a high speed signal are provided to efficiency process high speed signal by changing processing speed according to the outside and inside of a programmable logic device. CONSTITUTION: A high speed signal processing apparatus generates sampling data by sampling an analog signal(710) The high speed signal processing apparatus processes sampling data in order to make the transfer rate of sampling data less than a first-transfer rate. The high speed signal processing apparatus processes sampling data in order to enhance the transfer rate of sampling data over a second transfer rate(720) The high speed signal processing apparatus changes the outputted sampling data into an analog signal(730).
摘要翻译：目的：提供一种用于处理高速信号的装置和方法，以通过根据可编程逻辑器件的外部和内部改变处理速度来高效处理高速信号。构成：高速信号处理装置通过对模拟信号进行采样来生成采样数据（710）高速信号处理装置处理采样数据，以使采样数据的传送速率小于第一传送速率。高速信号处理装置处理采样数据，以提高采样数据在第二传送速率上的传送速率（720）。高速信号处理装置将输出的采样数据改变为模拟信号（730）。

13. 发明公开

KR1020100084746A ＳＡＲ 아날로그 디지털 변환기 失效
标题翻译：数字近似寄存器模拟到数字转换器和后续逼近寄存器模拟到数字转换方法
公开(公告)号：KR1020100084746A
公开(公告)日：2010-07-28
申请号：KR1020090004052
申请日：2009-01-19
申请人： 한국과학기술원
发明人： 유회준 , 김빈희
IPC分类号： H03M1/12 , H03M1/66
CPC分类号： H03M1/1245 , H03M1/403 , H03M1/66 , H03M2201/2291 , H03M2201/61 , H03M2201/8152
摘要： PURPOSE: A SAR analog to digital converter and conversion method can diminish the switching energy and total capacitor size by offering the sampling value to the bi node of comparator to the respective other equation. CONSTITUTION: It is input the analog input signal and the capacitor array part(100) samples the analog input voltage, the reference voltage and difference voltage of the analog input voltage. The capacitor array part stores the analog input voltage. It is input the analog input voltage and the sampled difference voltage in the respective first input node and the second input shift and the comparison unit compares the analog input voltage and difference voltage.
摘要翻译：目的：SAR模数转换器和转换方法可以通过将比较器的双节点的采样值提供给相应的其他等式来减小开关能量和总电容大小。构成：输入模拟输入信号，电容阵列部分（100）对模拟输入电压，模拟输入电压的参考电压和差分电压进行采样。电容器阵列部分存储模拟输入电压。在相应的第一输入节点和第二输入移位中输入模拟输入电压和采样的差分电压，比较单元比较模拟输入电压和差分电压。

14. 发明公开

KR1020080068011A 완전 차동형 비교기 및 완전 차동형 증폭회로 无效
标题翻译：全差分比较器和全差分放大器
公开(公告)号：KR1020080068011A
公开(公告)日：2008-07-22
申请号：KR1020087007902
申请日：2006-08-31
申请人： 파나소닉 주식회사
发明人： 히구치마사히로
IPC分类号： H03K5/22 , H03K3/45 , H03M1/12
CPC分类号： H03M1/1245 , H03F3/005 , H03F3/45475 , H03F3/45968 , H03F2203/45134 , H03F2203/45212 , H03K5/2481 , H03K5/249
摘要： A first to a fourth sampling switch (1a to 1d), a first to a fourth sampling capacitor (4 to 7), and a first and a second charge redistribution switch (2a, 2b) are provided on the input side of a differential amplifier (8). A first and a second reset switch (3a, 3b) are provided between the input and the output of the differential amplifier (8). An input signal voltage (Vinp) having a positive polarity, a comparison reference voltage (Vrefn) having a negative polarity, a comparison reference voltage (Vrefp) having a positive polarity, and an input signal voltage (Vinn) having a negative polarity are respectively applied through a first to a fourth sampling switch (1a to 1d) to one end of each of the first to the fourth sampling capacitor (4 to 7). During a reset period, the reset of the differential amplifier (8) is released after sampling of each voltage is completed, and during a comparison period, the first and the second charge redistribution switch (2a, 2b) are electrically connected.
摘要翻译：第一至第四采样开关（1a至1d），第一至第四采样电容器（4至7）以及第一和第二充电再分配开关（2a，2b）设置在差分放大器的输入侧（8）。第一和第二复位开关（3a，3b）设置在差分放大器（8）的输入和输出之间。具有正极性的输入信号电压（Vinp），具有负极性的比较参考电压（Vrefn），具有正极性的比较参考电压（Vrefp）和具有负极性的输入信号电压（Vinn）分别是通过第一至第四采样开关（1a至1d）施加到第一至第四采样电容器（4至7）中的每一个的一端。在复位期间，在各电压的取样完成之后，差分放大器（8）的复位被解除，在比较期间，第一和第二充电再分配开关（2a，2b）电连接。

15. 发明公开

KR1020070065366A 샘플 홀드 회로 및 그것을 이용한 파이프라인 ＡＤ 변환기 无效
标题翻译：样品保持电路和使用电路的管路AD转换器
公开(公告)号：KR1020070065366A
公开(公告)日：2007-06-22
申请号：KR1020077008231
申请日：2005-10-12
申请人： 소니 주식회사
发明人： 오노,고이찌 , 세가미,마사히로
IPC分类号： H03M1/14 , H03M1/12
CPC分类号： H03F3/45717 , G11C27/026 , H03F2203/45634 , H03F2203/45726 , H03M1/1245 , H03M1/145
摘要： A switched capacitor sample hold circuit using a source-earthed input operation amplifier. This operation circuit is provided with a feed forward circuit or a feedback circuit, which is connected with a feedback capacitor of the operation amplifier through a switch. An input common voltage or the middle point voltage of an output is detected to precharge the feedback capacitor beforehand with the difference from a reference voltage thereby to suppress fluctuations in an output operation point at the time of amplifying the operation amplifier.
摘要翻译：使用源极接地输入运算放大器的开关电容器采样保持电路。该运算电路具有通过开关与运算放大器的反馈电容器连接的前馈电路或反馈电路。检测输出公共电压或输出的中点电压，以预先用与参考电压的差预充电反馈电容，从而抑制放大运算放大器时的输出运算点的波动。

16. 发明公开

KR1020070008132A 선형뺄셈기를 이용한 저전력 전압 증폭기 및 이를 이용한아날로그-디지털 변환기 无效
标题翻译：使用线性放大器的低功耗电压放大器，并使用数字转换器进行模拟
公开(公告)号：KR1020070008132A
公开(公告)日：2007-01-17
申请号：KR1020050063117
申请日：2005-07-13
申请人： 고려대학교 산학협력단
发明人： 김수원 , 김길수
IPC分类号： H03F3/00 , H03M1/12
CPC分类号： H03F1/223 , G06G7/14 , H03F3/45192 , H03M1/1245
摘要： A low power voltage amplifier using a linear subtracter is provided to control an output time of an output signal by using a delay element for each stage of the low power voltage amplifier. In a low power voltage amplifier using a linear subtracter, the linear subtracter(30) outputs a difference of signals which are inputted into two input stages. One input stage of the linear subtracter is connected to a power voltage and the other input stage of the linear subtracter is connected to a first input signal(Vin1). A first PMOS(P-channel Metal-Oxide Semi-conductor) transistor(M3) has a source stage which is connected to an output signal and a bulk node. A second PMOS transistor(M4) has the same source-gate voltage with a source-gate voltage of the first PMOS transistor.
摘要翻译：提供使用线性减法器的低功率电压放大器，通过使用低功率电压放大器的各级的延迟元件来控制输出信号的输出时间。在使用线性减法器的低功率电压放大器中，线性减法器（30）输出输入到两个输入级的信号差。线性减法器的一个输入级连接到电源电压，线性减法器的另一输入级连接到第一输入信号（Vin1）。第一PMOS（P沟道金属氧化物半导体）晶体管（M3）具有连接到输出信号和体节点的源级。第二PMOS晶体管（M4）具有与第一PMOS晶体管的源极栅极电压相同的源栅极电压。

17. 发明公开

KR1020060099018A 샘플링/홀딩용 증폭기 无效
标题翻译：放大器用于采样和控制
公开(公告)号：KR1020060099018A
公开(公告)日：2006-09-19
申请号：KR1020050019990
申请日：2005-03-10
申请人： 엘지전자 주식회사
发明人： 이우열
IPC分类号： H03M1/66 , H03F3/45
CPC分类号： H03M1/1245 , G02F1/133 , H03F3/45 , H03M2201/61 , H03M2201/625 , H03M2201/932
摘要： 본 발명은 아날로그 그래픽 신호를 샘플링 및 홀딩하여 증폭하는 샘플링/홀딩용 증폭기로 12비트 이상의 고해상도와, 100㎒ 이상의 고속 동작을 만족한다.
12비트 이상의 높은 해상도를 얻기 위하여 2단 증폭기로 아날로그 그래픽 신호를 2단 증폭하고, 아날로그 그래픽 신호를 2단 증폭하면서 높은 이득을 얻을 수 있도록 부스팅용 증폭기를 구비하여 이득을 증가시키고, 100㎒ 이상의 고속으로 동작할 수 있도록 하는 것으로서 제 1 바이어스 전압에 따라 소정 레벨의 정전류가 흐르는 제 1 정전류원과, 상기 정전류원에 의해 정전류가 흐르면서 입력단자로 입력되는 아날로그 그래픽 신호를 차동 증폭하는 제 1 증폭기와, 상기 차동 증폭기의 출력신호를 증폭하여 출력단자로 출력하는 제 2 증폭기와, 상기 제 2 증폭기의 증폭이득을 증가시키는 제 1 및 제 2 부스팅용 증폭기로 구성하여 고화질과, 콘트라스트 및 밝기가 향상된다.
아날로그/디지털 변환기, 샘플링/홀딩용 증폭기, 고해상도, 모니터

18. 发明公开

KR1020000044573A 아날로그-디지털변환기 有权
标题翻译：模拟数字转换器
公开(公告)号：KR1020000044573A
公开(公告)日：2000-07-15
申请号：KR1019980061072
申请日：1998-12-30
申请人： 매그나칩 반도체 유한회사
发明人： 황성욱 , 송정우
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/1245 , H03M1/145
摘要： PURPOSE: An analog-to-digital converter is provided to improve a total signal process speed by performing a reference voltage sampling period prior to an analog signal input period so as to remove a holding time at an intermediate bit portion. CONSTITUTION: An analog-to-digital converter comprises a sample and hold amplifier(51) which samples an analog signal(SA) during a sample period(S) and holds the sampled signal during a hold period(H). An upper-bit A/D converting part(52) samples a reference voltage during the sample time(S) of the amplifier(51), and receives the sampled analog signal to output a digital code of N upper bits during the hold time(H). The upper-bit A/D converting part(52) generates a control signal so as to select a first fine reference voltage region. A resistor string(53) selects a first fine reference voltage signal according to the control signal. An intermediate-bit A/D converting part(54) receives the sampled analog signals from the converting part(52) and the amplifier(51) during the hold time(H), and compares the inputted analog signals with the first fine reference voltage to generate a digital signal of (N+1) intermediate bits. First and second lower-bit A/D converting parts(55,57) receive the sampled analog signals from the converting part(52) and the amplifier(51) during the hold time(H), and compare the inputted analog signals with a first fine reference voltage selected by a second resistor string(56) during a next period(C) to generate a digital signal of (N+1) intermediate bits as the result. A digital correction part(58) receives the digital signal of the N upper bits and either one of outputs of the converting parts(54,55,57) to output a digital code of 3N bits.
摘要翻译：目的：提供模数转换器，通过在模拟信号输入周期之前执行参考电压采样周期来提高总信号处理速度，以消除中间位部分的保持时间。构成：模数转换器包括在采样周期（S）期间采样模拟信号（SA）的采样和保持放大器（51），并在保持时段（H）期间保持采样信号。高位A / D转换部分（52）在放大器（51）的采样时间（S）期间对参考电压进行采样，并且在保持时间期间接收采样的模拟信号以输出N个高位数字码 H）。高位A / D变换部（52）产生控制信号，以选择第一精细基准电压区域。电阻串（53）根据控制信号选择第一精细基准电压信号。中间位A / D转换部分（54）在保持时间（H）期间从转换部分（52）和放大器（51）接收采样的模拟信号，并将输入的模拟信号与第一精细参考电压以产生（N + 1）个中间比特的数字信号。第一和第二低位A / D转换部分（55,57）在保持时间（H）期间从转换部分（52）和放大器（51）接收采样的模拟信号，并将输入的模拟信号与在下一个周期（C）期间由第二电阻串（56）选择的第一精细参考电压，以产生作为结果的（N + 1）个中间位的数字信号。数字校正部分（58）接收N个高位的数字信号和转换部分（54,55,57）的输出中的任一个，以输出3N位的数字码。

19. 发明授权

KR101879328B1 이중 분리형 단조 연속 근사 아날로그 디지털 변환기 有权
公开(公告)号：KR101879328B1
公开(公告)日：2018-07-18
申请号：KR1020170029312
申请日：2017-03-08
申请人： 충북대학교 산학협력단
发明人： 양병도 , 우기찬 , 김태우 , 황선광 , 김미정
IPC分类号： H03M1/38 , H03M1/12
CPC分类号： H03M1/38 , H03M1/1245 , H03M2201/62 , H03M2201/8152
摘要： 본발명은이중분리형단조연속근사아날로그디지털변환기에관한것으로서, 연속근사레지스터(SAR) 제어로직에의해스위칭제어에대응하여입력신호인제1입력신호(V)와제2입력신호(V)를입력받아샘플동작및 홀드동작을수행하는샘플홀드부와, 샘플홀드시간동안제1입력신호와제2입력신호에대해각각에대응되는출력전압값인제1출력신호와제2출력신호로생성하며, 2개의브리지커패시터(C, C)를이용하여상위비트또는하위비트를결정하기위한커패시터어레이를 2단구조로형성한커패시터어레이와, 샘플홀드부와연동되어상위비트또는하위비트를결정하는스위치(S7, LSB_SW)와, 제1출력신호와제2출력신호의크기를비교하여비교결과에따라디지털값을출력하는비교기와, 디지털값에대응하여최종디지털코드값을결과신호로출력하는연속근사레지스터제어로직을포함한다. 본발명에따르면, 이중분리형과단조를조합하여커패시터개수감소, 에너지효율향상, 커패시터크기구현가능, 정확도향상등의효과를기대할수 있다.

20. 发明公开

KR20180028891A 교정 시스템 및 방법 审中-公开
标题翻译：校准系统和方法
公开(公告)号：KR20180028891A
公开(公告)日：2018-03-19
申请号：KR20170034378
申请日：2017-03-20
IPC分类号： G04F10/00 , H03M1/10 , H03M1/38
CPC分类号： H03M1/1009 , G04F10/005 , G06F17/5081 , H03L7/087 , H03L7/0995 , H03M1/1245 , H03M1/183 , H03M1/38
摘要： 교정시스템및 방법이제공된다. 교정시스템은, 카운터어레이, 카운터어레이와전기적으로연결되는링 오실레이터, 링오실레이터와전기적으로연결되는 ADC(analog-to-digital converter) 드라이버및 ADC 드라이버와전기적으로연결되는 ADC를포함하고, 카운터어레이는링 오실레이터의사이클수를카운팅하고, ADC의출력은링 오실레이터에전기적으로연결된다.
摘要翻译：一种设备和方法。该装置包括计数器阵列; 环形振荡器，其电耦合到所述计数器阵列，其中所述计数器阵列对所述环形振荡器中的多个周期进行计数; 电耦合到环形振荡器的模数转换器（ADC）驱动器; 以及电耦合到ADC驱动器的ADC，其中ADC的输出电耦合到环形振荡器。

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