专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明公开

KR1020010074408A 이동통신 제어국 시스템에서 호 처리 프로세서의 프로그램로딩방법 无效
标题翻译：移动通信基站控制系统的呼叫控制处理器（CCP）的程序加载方法
公开(公告)号：KR1020010074408A
公开(公告)日：2001-08-04
申请号：KR1020000003472
申请日：2000-01-25
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 임병민 , 김선희
IPC分类号： H04W88/18 , H04W88/12
摘要： PURPOSE: A program loading method for a call control processor(CCP) of a mobile communication base station controller system is provided to increase the reliability of a system and efficiently operate the system by receiving new programs using a standby side and operating the received programs when a new software is applied to the system. CONSTITUTION: A CCP program is loaded in an active side and a standby side(S101). A CCP standby side is restarted, and new programs are loaded from a BSM(Base Station Manager)(S102). After the loading of the standby side is completed, a standby processor is operated as an active processor(S103). It is judged whether a CCP is upgraded using new programs(S104). A processor having previous programs is restarted, and a new software is loaded from the BSM and the processor is operated as a standby processor state(S105). A processor operated as a current standby is switched to the active processor and the processor is operated as the active processor(S106).
摘要翻译：目的：提供一种用于移动通信基站控制器系统的呼叫控制处理器（CCP）的程序加载方法，以增加系统的可靠性并通过使用待机侧接收新程序并有效地操作该系统，并且当一个新的软件被应用于系统。构成：在主动侧和待机侧装载CCP程序（S101）。重新启动CCP备用端，并从BSM（基站管理器）加载新程序（S102）。在待机侧的装载完成之后，作为活动处理器操作备用处理器（S103）。判断是否使用新程序升级CCP（S104）。重新开始具有先前程序的处理器，并且从BSM加载新的软件，并且处理器作为待机处理器状态运行（S105）。作为当前待机操作的处理器被切换到活动处理器，并且处理器作为活动处理器操作（S106）。

12. 发明公开

KR1020120036429A 인쇄회로기판 형성 방법 无效
标题翻译：形成印刷电路板的方法
公开(公告)号：KR1020120036429A
公开(公告)日：2012-04-18
申请号：KR1020100098093
申请日：2010-10-08
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 김현석 , 정부호 , 조선기 , 김양희 , 김영원
IPC分类号： H05K9/00 , H05K3/32
摘要： PURPOSE: A method for forming a printed circuit board is provided to reduce distortion of a signal inputted to a signal line by suppressing noises applied to a power voltage and a ground voltage. CONSTITUTION: A wire connected to a signal, a power voltage, and a ground voltage is formed on a substrate(10). A signal line unit(20) includes a first signal line(21) and a second signal line(22). A power line unit(30) includes a first power line unit(31) and a second power line unit(32). The first power line unit includes a first power line(31a), a first via(31b), and a first plate(31c). The second power line unit includes a second power line(32a), a second via(32b), and a second plate(32c).
摘要翻译：目的：提供一种用于形成印刷电路板的方法，以通过抑制施加于电源电压和接地电压的噪声来减少输入到信号线的信号的失真。构成：在基板（10）上形成连接到信号，电源电压和接地电压的电线。信号线单元（20）包括第一信号线（21）和第二信号线（22）。电力线单元（30）包括第一电力线单元（31）和第二电力线单元（32）。第一电力线单元包括第一电力线（31a），第一通孔（31b）和第一板（31c）。第二电力线单元包括第二电力线（32a），第二通孔（32b）和第二板（32c）。

13. 发明公开

KR1020120019690A 캐패시터 형성 방법과 이를 이용한 반도체 소자 无效
标题翻译：用于形成电容器和使用该电容器的半导体器件的方法
公开(公告)号：KR1020120019690A
公开(公告)日：2012-03-07
申请号：KR1020100083052
申请日：2010-08-26
申请人： 에스케이하이닉스 주식회사
发明人： 김현석 , 이준호 , 정부호 , 조선기 , 김양희 , 김영원
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/90 , H01L27/0808 , H01L27/0811 , H01L29/94
摘要： PURPOSE: A method for forming a capacitor and a semiconductor device using the same are provided to improve the noise attenuation efficiency of a decoupling capacitor by decreasing the resistance of a wire which connects the decoupling capacitor to a power voltage. CONSTITUTION: A first MOS capacitor(MOS_CP1) includes a first gate and a first source/drain. A second MOS capacitor(MOS_ CP2) includes a second gate and a second source/drain. A first cylinder capacitor(CYL_CP1) includes a top electrode, a first dielectric layer, and a first bottom electrode. A second cylinder capacitor(CYL_CP2) includes a top electrode, a second dielectric layer, and a second bottom electrode. A metal wire(10A,10B) connects the gate to the bottom electrode.
摘要翻译：目的：提供一种用于形成电容器的方法和使用该电容器的半导体器件，以通过降低将去耦电容器连接到电源电压的电线的电阻来改善去耦电容器的噪声衰减效率。构成：第一MOS电容器（MOS_CP1）包括第一栅极和第一源极/漏极。第二MOS电容器（MOS_CP2）包括第二栅极和第二源极/漏极。第一气缸电容器（CYL_CP1）包括顶电极，第一电介质层和第一底电极。第二气缸电容器（CYL_CP2）包括顶电极，第二电介质层和第二底电极。金属线（10A，10B）将栅极连接到底部电极。

14. 发明授权

KR101086856B1 반도체 집적 회로 모듈 및 이를 구비하는 ＰＣＢ 장치 失效
标题翻译：半导体集成电路模块和PCB设备
公开(公告)号：KR101086856B1
公开(公告)日：2011-11-25
申请号：KR1020080035229
申请日：2008-04-16
申请人： 에스케이하이닉스 주식회사
发明人： 이준호
IPC分类号： H05K1/02
CPC分类号： H05K1/0245 , H05K1/0236 , H05K2201/09236 , H05K2201/09309 , H05K2201/09663 , H05K2201/09681
摘要： 본 발명의 PCB(Printed Circuit Board) 장치는, 반도체 집적 회로 칩에 차동 신호 쌍을 제공하는 차동 신호 라인 쌍을 구비하는 신호 라인 층; 상기 신호 라인 층의 하층부에 배치되는 EBG(Electromagnetic Bandgap) 패턴 층; 및 상기 신호 라인 층과 상기 EBG 패턴 층 사이에 배치되는 절연 층;을 포함하는 것을 특징으로 한다.
반도체 집적 회로, EBG 패턴, 차동 신호 쌍

15. 发明授权

KR101062848B1 관통실리콘비아를 갖는 반도체칩에서 크로스토크 차폐를 위한 쉴딩구조 有权
公开(公告)号：KR101062848B1
公开(公告)日：2011-09-07
申请号：KR1020090048140
申请日：2009-06-01
申请人： 에스케이하이닉스 주식회사 , 한국과학기술원
发明人： 이준호 , 이형동 , 김현석 , 김정호 , 김가원 , 조종현 , 이상록
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： 본 발명은 관통실리콘비아간의 크로스토크를 차폐하고 기판노이즈를 최소화할 수 있는 반도체칩을 제공하기 위한 것으로, 본 발명의 반도체칩은 실리콘기판; 상기 실리콘기판을 관통하는 복수의 관통실리콘비아; 및 적어도 어느 하나의 상기 관통실리콘비아의 주변을 에워싸는 크로스토크쉴딩부를 포함하고, 상술한 본 발명은 관통실리콘비아의 주변을 에워싸는 크로스토크쉴딩부를 구비함으로써 관통실리콘비아간의 크로스토크를 방지할 수 있는 효과가 있으며, 또한, 본 발명은 캐패시터를 이용하여 관통실리콘비아의 주변을 에워쌈으로써 관통실리콘비아간의 크로스토크 및 기판노이즈를 방지할 수 있는 효과가 있다.
반도체패키지, 관통실리콘비아, 크로스토크, 노이즈, 인터비아

16. 发明授权

KR101047061B1 반도체 장치의 출력 회로 失效
标题翻译：半导体存储器的输出电路
公开(公告)号：KR101047061B1
公开(公告)日：2011-07-06
申请号：KR1020100009911
申请日：2010-02-03
申请人： 에스케이하이닉스 주식회사
发明人： 정부호 , 이준호 , 김현석 , 김양희
IPC分类号： G11C7/10 , G11C11/21 , G11C11/24
CPC分类号： H01L25/00 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE: An output circuit of a semiconductor memory apparatus is provided to minimize power noise in all frequency bands by arranging first and second capacitors which have different properties. CONSTITUTION: First and second pads(112,114) supply a power voltage and a ground voltage. A main output part(120) provides the power voltage and the ground voltage from the first and second pads. One end of a decoupling capacitor area(130a) is connected to the first pad. The other end of the decoupling capacitor area is connected to the second pad. The decoupling capacitor area comprises first and second decoupling capacitor areas. The first decoupling capacitor area is formed by a first distance from a part of the main output unit. The second decoupling capacitor area is formed by a second distance from the main output unit. The second distance is longer than the first distance.
摘要翻译：目的：提供半导体存储装置的输出电路，通过布置具有不同性质的第一和第二电容器来最小化所有频带的功率噪声。构成：第一和第二焊盘（112,114）提供电源电压和接地电压。主输出部分（120）提供来自第一和第二焊盘的电源电压和接地电压。去耦电容器区域（130a）的一端连接到第一焊盘。去耦电容器区域的另一端连接到第二焊盘。去耦电容器区域包括第一和第二去耦电容器区域。第一去耦电容器区域由与主输出单元的一部分的第一距离形成。第二去耦电容器区域与主输出单元形成第二距离。第二距离比第一距离长。

17. 发明授权

KR101046275B1 파워 메쉬 구조를 갖는 반도체 메모리 장치 失效
标题翻译：半导体存储器包括功率结构
公开(公告)号：KR101046275B1
公开(公告)日：2011-07-04
申请号：KR1020100027820
申请日：2010-03-29
申请人： 에스케이하이닉스 주식회사
发明人： 정부호 , 이준호 , 김현석 , 조선기 , 김양희 , 김영원
IPC分类号： G11C8/14 , G11C7/18 , G11C8/12 , H01L21/28
CPC分类号： G11C5/063 , G11C5/025 , G11C7/06 , G11C8/08 , G11C8/14
摘要： PURPOSE: A semiconductor memory apparatus including a power-meshed structure is provided to improve power supply capability by connecting a plate electrode or a stable pattern to a power line connected to a column control block. CONSTITUTION: A plurality of banks comprises a semiconductor memory device for having a plurality of cell mat power mesh structures. A plurality of power lines are arranged in the prescribed part of a plurality of banks. A column control area is arranged in at least one region of the edge of the bank. A conductive plate is arranged on the top side of a column control region. The conductive plate is electrically connected to the plural power lines.
摘要翻译：目的：提供一种包括电源网格结构的半导体存储装置，通过将平板电极或稳定图案连接到连接到列控制块的电力线来提高电力供应能力。构成：多个存储体包括用于具有多个电池垫功率网格结构的半导体存储器件。多个电源线布置在多个银行的规定部分中。列控制区域布置在堤岸的边缘的至少一个区域中。导电板设置在列控制区域的顶侧。导电板电连接到多条电源线。

18. 发明公开

KR1020100076502A 반도체 장치 및 그를 포함하는 반도체 패키지 失效
标题翻译：半导体器件和半导体封装，包括它们
公开(公告)号：KR1020100076502A
公开(公告)日：2010-07-06
申请号：KR1020080134579
申请日：2008-12-26
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 이형동 , 김현석
IPC分类号： H01L27/04 , H01L23/52
CPC分类号： H01L23/5223 , H01G4/232 , H01G4/30 , H01G4/33 , H01G4/40 , H01L23/3128 , H01L23/481 , H01L23/642 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/15311 , H01L2924/19104 , H01L2224/05099
摘要： PURPOSE: A semiconductor device and a semiconductor package comprising the same are provided to increase the capacitance of a decoupling capacitor without an area increase by forming the decoupling capacitor on a separate semiconductor chip. CONSTITUTION: A semiconductor device(200) comprises first and second semiconductor chips(301,307). The first semiconductor chip comprises a decoupling capacitor(305). One end of the decoupling capacitor is connected to a power supply voltage and the other end is electrically connected to a ground voltage. The decoupling capacitor is electrically connected to the power supply pad and the ground pad of the first semiconductor chip. The second semiconductor chip is electrically connected to the first semiconductor chip through via(311) formed in the second semiconductor chip.
摘要翻译：目的：提供半导体器件和包括该半导体器件的半导体封装，以通过在单独的半导体芯片上形成去耦电容器来增加去耦电容器的电容而不增加面积。构成：半导体器件（200）包括第一和第二半导体芯片（301,307）。第一半导体芯片包括去耦电容器（305）。去耦电容器的一端连接到电源电压，另一端电连接到接地电压。去耦电容器电连接到第一半导体芯片的电源焊盘和接地焊盘。第二半导体芯片通过形成在第二半导体芯片中的通孔（311）与第一半导体芯片电连接。

19. 发明公开

KR1020080061950A 전자기 밴드갭 전원 전달 시스템을 가진 멀티 레이어 기판 无效
标题翻译：具有电磁带传输系统的多层板
公开(公告)号：KR1020080061950A
公开(公告)日：2008-07-03
申请号：KR1020060137161
申请日：2006-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 이준호
IPC分类号： H05K3/46
CPC分类号： H05K1/0236 , H05K1/115 , H05K2201/093
摘要： A multi-layer substrate having an EBG PDS(Electromagnetic Band Gap Power Delivery System) is provided to implement the partial EBG PDS without an additional conductive layer by utilizing a signal layer, a power layer, or a ground layer. A multi-layer substrate having an EBG PDS includes a signal layer(S_TOP), a first power/ground layer(P/G_1), an EBG patch, and a second power/ground layer(P/G_2). The first power/ground layer is connected to some region(100) of the signal layer through a first via(110). The EBG patch is patterned in some region(C) of the first power/ground layer corresponding to some region of the signal layer. The second power/ground layer is connected to the EBG patch through a second via.
摘要翻译：提供具有EBG PDS（电磁带隙电力输送系统）的多层基板，以通过利用信号层，功率层或接地层来实现部分EBG PDS而不需要额外的导电层。具有EBG PDS的多层基板包括信号层（S_TOP），第一电源/接地层（P / G_1），EBG贴片和第二电源/接地层（P / G_2）。第一电源/接地层通过第一通孔（110）连接到信号层的一些区域（100）。 EBG贴片在对应于信号层的某个区域的第一电力/接地层的某些区域（C）中被图案化。第二电源/接地层通过第二通孔连接到EBG补丁。

20. 发明授权

KR101940110B1 반도체 장치의 출력 데이터 노이즈 제거 방법 및 이를 구현하는 반도체 장치 有权
公开(公告)号：KR101940110B1
公开(公告)日：2019-01-18
申请号：KR1020120095552
申请日：2012-08-30
申请人： 에스케이하이닉스 주식회사
发明人： 한성우 , 오익수 , 이준호 , 정부호 , 조선기 , 김양희 , 김태훈
IPC分类号： G11C7/10

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式