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11. 发明公开

KR1020030054268A 반도체소자의 제조방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020030054268A
公开(公告)日：2003-07-02
申请号：KR1020010084404
申请日：2001-12-24
申请人： 에스케이하이닉스 주식회사
发明人： 이명신
IPC分类号： H01L21/3205
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing the generation of voids in an interlayer dielectric by improving the forming step of the interlayer dielectric. CONSTITUTION: The first interlayer dielectric(140a) is formed at the upper portion of a semiconductor substrate(100), wherein the semiconductor substrate has a plurality of bit lines(110). The upper portion of the first interlayer dielectric is removed by carrying out a wet etching process for removing the voids generated at the upper portion of the first interlayer dielectric. Then, an interlayer dielectric pattern is formed by depositing the second interlayer dielectric(140b) on the entire surface of the resultant structure. Preferably, the second interlayer dielectric is formed by using the same material used for forming the first interlayer dielectric.
摘要翻译：目的：提供一种制造半导体器件的方法，通过改进层间电介质的形成步骤，能够防止在层间电介质中产生空隙。构成：第一层间电介质（140a）形成在半导体衬底（100）的上部，其中半导体衬底具有多个位线（110）。通过执行用于去除在第一层间电介质的上部处产生的空隙的湿蚀刻工艺来去除第一层间电介质的上部。然后，通过在所得结构的整个表面上沉积第二层间电介质（140b）来形成层间电介质图案。优选地，通过使用用于形成第一层间电介质的相同材料形成第二层间电介质。

12. 发明公开

KR1020030050848A 반도체소자의 커패시터 제조방법 失效
标题翻译：制造半导体器件电容器的方法
公开(公告)号：KR1020030050848A
公开(公告)日：2003-06-25
申请号：KR1020010081383
申请日：2001-12-19
申请人： 에스케이하이닉스 주식회사
发明人： 이명신
IPC分类号： H01L27/108
摘要： PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of preventing the damage of the lower surface of a contact hole when removing a hard mask. CONSTITUTION: After sequentially depositing an interlayer dielectric(130) and a hard mask on a semiconductor substrate(100) having a plurality of bit lines(110), the first photoresist pattern is formed on the resultant structure. After forming a plurality of storage node contact holes by carrying out an etching process using the first photoresist pattern as an etching mask, the second photoresist layer is coated on the resultant structure. After exposing the hard mask by etching the second photoresist layer, the hard mask is removed by using the second photoresist layer as an etching stop layer. After removing the remaining second photoresist layer, a plurality of lower electrodes(180) for the storage node are formed at the resultant structure.
摘要翻译：目的：提供一种制造半导体器件的电容器的方法，以能够在去除硬掩模时防止接触孔的下表面的损坏。构成：在具有多个位线（110）的半导体衬底（100）上顺序沉积层间电介质（130）和硬掩模之后，在所得结构上形成第一光致抗蚀剂图案。在通过使用第一光致抗蚀剂图案作为蚀刻掩模进行蚀刻工艺形成多个存储节点接触孔之后，在所得到的结构上涂覆第二光致抗蚀剂层。在通过蚀刻第二光致抗蚀剂层暴露硬掩模之后，通过使用第二光致抗蚀剂层作为蚀刻停止层来去除硬掩模。在去除剩余的第二光致抗蚀剂层之后，在所得结构处形成用于存储节点的多个下电极（180）。

13. 发明公开

KR1020000043915A 반도체 소자의 제조 방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020000043915A
公开(公告)日：2000-07-15
申请号：KR1019980060353
申请日：1998-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 안기철 , 이명신
IPC分类号： H01L21/31
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to perform easily a succeeding process by improving a process for forming a capacitor lower electrode. CONSTITUTION: A method for manufacturing a semiconductor device comprises the following steps. A semiconductor substrate(20) is formed with a transistor and a bit line(24) on a cell region(A) and a peripheral circuit region(B). A nitride layer and an insulating layer are deposited on the bit line. A portion for forming a capacitor is defined on the cell region. A polysilicon for a capacitor lower electrode is deposited on a whole structure. The polysilicon for the capacitor lower electrode is removed. A gap fill oxide layer is deposited thereon. The gap fill oxide layer is remained only on a gap portion of a lower electrode polysilicon by etching the gap fill oxide layer. The capacitor lower electrode is completed by etching an exposed portion of the capacitor lower electrode. The gap fill oxide layer and the oxide layer for forming the capacitor are removed simultaneously and the nitride layer is removed. A dielectric layer(31) and a capacitor upper electrode(32) are formed on the cell region in order to complete the capacitor.
摘要翻译：目的：提供一种用于制造半导体器件的方法，通过改进形成电容器下电极的工艺来容易地执行后续处理。构成：制造半导体器件的方法包括以下步骤。半导体衬底（20）在单元区域（A）和外围电路区域（B）上形成有晶体管和位线（24）。氮化物层和绝缘层沉积在位线上。形成电容器的部分被限定在电池区域上。用于电容器下电极的多晶硅沉积在整个结构上。去除电容器下电极的多晶硅。在其上沉积间隙填充氧化物层。通过蚀刻间隙填充氧化物层，间隙填充氧化物层仅保留在下电极多晶硅的间隙部分上。通过蚀刻电容器下电极的暴露部分来完成电容器下电极。间隙填充氧化物层和用于形成电容器的氧化物层被同时去除并且氮化物层被去除。为了完成电容器，在单元区域上形成电介质层（31）和电容器上电极（32）。

14. 发明授权

KR100558048B1 반도체 소자의 비피에스지막 형성 방법 失效
标题翻译：在半导体器件中形成BPSG薄膜的方法
公开(公告)号：KR100558048B1
公开(公告)日：2006-03-07
申请号：KR1019990025448
申请日：1999-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 문영화 , 이명신
IPC分类号： H01L21/312
摘要： 본 발명은 반도체 소자의 비피에스지막 형성 방법에 관한 것으로, 고농도 BPSG 증착 후 BPSG 상에 산화막을 형성한 다음 고온 열처리 공정을 수행하므로써, 고농도 BPSG막으로부터 보론 및 인 이온이 외부배출되어 열처리 장비 내에 흡착되는 것을 방지하여, BPSG막의 증착 특성을 향상시키고 열처리 장비의 사용 효율을 증대시킬 수 있는 반도체 소자의 비피에스지막 형성 방법이 개시된다.
고농도 BPSG, 산화막

15. 发明公开

KR1020040059811A 반도체 소자의 랜딩 플러그 콘택 형성방법 无效
标题翻译：用于形成半导体器件的接线插头的方法
公开(公告)号：KR1020040059811A
公开(公告)日：2004-07-06
申请号：KR1020020086315
申请日：2002-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 이명신
IPC分类号： H01L21/28
摘要： PURPOSE: A method for forming a landing plug contact of a semiconductor device is provided to prevent bridge between plugs by restraining dishing of a BPSG and LPP(Land Plug Polysilicon) layer. CONSTITUTION: Gates(13) with a gate oxide layer(12), a nitride layer(14) and a spacer(15) are formed on a semiconductor substrate(10). A BPSG layer(16) is formed on the resultant structure. Contact holes are formed by selectively etching the BPSG layer. An LPP layer is filled in the contact holes. A bar type contact is formed by first CMP the LPP layer and the BPSG layer to expose the nitride layer using an alkali-based slurry. LPCs(Landing Plug Contacts)(18A1,18A2,18A3) are then formed by second CMP the bar type contact, the BPSG layer and the nitride layer using an acid-based slurry.
摘要翻译：目的：提供一种用于形成半导体器件的着陆插头接触的方法，以通过限制BPSG和LPP（Land Plug Polysilon）层的凹陷来防止插头之间的桥接。构成：在半导体衬底（10）上形成具有栅极氧化物层（12），氮化物层（14）和间隔物（15）的栅极（13）。在所得结构上形成BPSG层（16）。通过选择性蚀刻BPSG层形成接触孔。 LPP层填充在接触孔中。通过第一CMP将LPP层和BPSG层形成条形接触，以使用碱性浆液露出氮化物层。然后通过第二CMP使用基于酸的浆料，通过棒状接触，BPSG层和氮化物层形成LPC（着陆插头触点）（18A1,18A2,18A3）。

16. 发明授权

KR100427718B1 반도체 소자의 제조 방법 失效
标题翻译： 반도체소자의제조방법
公开(公告)号：KR100427718B1
公开(公告)日：2004-04-28
申请号：KR1020020037694
申请日：2002-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 이명신
IPC分类号： H01L21/28
摘要： PURPOSE: A method for fabricating a semiconductor device is provided to prevent a tungsten layer of a metal gate electrode from being exposed, by forming the tungsten layer on a polycrystalline silicon layer for forming a landing plug, by etching the tungsten layer of a cell part and the upper portion of the polycrystalline silicon layer and by performing a chemical mechanical polishing(CMP) process of forming the landing plug. CONSTITUTION: An interlayer dielectric(45) is formed on a lower structure wherein the cell part and a peripheral part are defined such that the lower structure includes a lower interconnection having a hard mask layer(39) in its upper portion. The interlayer dielectric is etched to form a contact hole for a plug in the cell part through a photolithography process using a mask for the plug. A polycrystalline silicon layer and a metal layer(51) are sequentially formed on the contact hole for the plug and the interlayer dielectric. The metal layer in the cell part is etched through a photolithography process using a mask including a light transmission part only in the cell part. The upper portion of the polycrystalline silicon layer in the cell part is etched to generate a step between the cell part and the peripheral part. The metal layer, the polycrystalline silicon layer and the interlayer dielectric are blanket-etched by using the hard mask layer as an etch barrier layer wherein a plug of the polycrystalline silicon layer is formed.
摘要翻译：目的：提供一种用于制造半导体器件的方法，用于通过刻蚀单元部分的钨层，通过在用于形成连接插塞的多晶硅层上形成钨层来防止金属栅电极的钨层暴露和多晶硅层的上部并且通过执行形成平台插塞的化学机械抛光（CMP）工艺。一种层间电介质（45）形成在下部结构上，其中电池部分和外围部分被限定成使得下部结构包括在其上部具有硬掩模层（39）的下部互连。通过使用用于插塞的掩模的光刻工艺来蚀刻层间电介质以形成用于电池部分中的插塞的接触孔。在用于插塞和层间电介质的接触孔上顺序地形成多晶硅层和金属层（51）。使用仅在单元部分中包括光透射部分的掩模，通过光刻工艺蚀刻单元部分中的金属层。蚀刻单元部分中的多晶硅层的上部以在单元部分和外围部分之间产生台阶。通过使用硬掩模层作为蚀刻阻挡层来毯式蚀刻金属层，多晶硅层和层间电介质，其中形成多晶硅层的栓塞。

17. 发明公开

KR1020020017097A 반도체 소자의 커패시터 형성 방법 无效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：KR1020020017097A
公开(公告)日：2002-03-07
申请号：KR1020000050189
申请日：2000-08-28
申请人： 에스케이하이닉스 주식회사
发明人： 이명신 , 임비오
IPC分类号： H01L27/108
摘要： PURPOSE: A method for forming a capacitor of a semiconductor device is provided to simplify manufacturing processes and to prevent the lifting of capacitors generated at edge portions of a wafer by using a thick silicon nitride as an etch stopper. CONSTITUTION: A planarized insulating layer(21) is formed on a semiconductor substrate having cell transistors. After forming a thick nitride layer on the planarized insulating layer(21), contact holes are formed by selectively etching the insulating layer(21) and the thick nitride layer. After sufficiently filling a polysilicon layer into the contact holes, a polysilicon plug(24) is formed by blanket etch-back processing. During the blanket etch-back processing, the thick nitride layer is simultaneously partial etched so as to form a thin silicon nitride layer(22a) while preventing capacitor lifting. Then, a lower electrode(27a) of the capacitor is formed.
摘要翻译：目的：提供一种用于形成半导体器件的电容器的方法，以简化制造工艺，并且通过使用厚氮化硅作为蚀刻停止器来防止在晶片的边缘部分产生的电容器的提升。构成：在具有单元晶体管的半导体衬底上形成平坦化的绝缘层（21）。在平坦化绝缘层（21）上形成厚氮化物层之后，通过选择性地蚀刻绝缘层（21）和厚氮化物层形成接触孔。在将多晶硅层充分地填充到接触孔中之后，通过毯式回蚀处理形成多晶硅插塞（24）。在覆盖层回蚀处理期间，同时对厚氮化物层进行部分蚀刻，以形成薄的氮化硅层（22a），同时防止电容器提升。然后，形成电容器的下电极（27a）。

18. 发明公开

KR1020010018071A 반도체 소자의 캐패시터 형성방법 失效
标题翻译：制造半导体器件电容器的方法
公开(公告)号：KR1020010018071A
公开(公告)日：2001-03-05
申请号：KR1019990033876
申请日：1999-08-17
申请人： 에스케이하이닉스 주식회사
发明人： 이명신 , 김춘환
IPC分类号： H01L21/108
摘要： PURPOSE: A method for manufacturing a capacitor is provided to eliminate a bridge problem between capacitors, by forming a SiON layer on an outer wall of a lower charge storage electrode. CONSTITUTION: After an interlayer dielectric(12) is formed on a semiconductor substrate(10) having various elements for forming a semiconductor device, the interlayer dielectric in a portion where a capacitor is to be formed is etched to form a contact hole. After the first polysilicon layer(13) for a plug is buried in the contact hole, a sacrificial oxide layer, an anti-reflecting coating(ARC) layer and a photoresist layer pattern are sequentially formed on the entire surface. An etching process is performed to expose the first polysilicon layer by using the photoresist layer pattern as a mask. The photoresist layer pattern is eliminated to form a pattern composed of the ARC layer and the sacrificial oxide layer. After a passivation layer is applied on the entire surface, an etching process is performed regarding the entire surface until the first polysilicon layer is exposed so that the ARC layer is removed and the passivation layer is left only on a side of the sacrificial oxide layer pattern. The second polysilicon layer(20) for a lower charge storage electrode is formed on the entire surface, and a photoresist layer is buried. After the photoresist layer is removed to expose the sacrificial oxide layer by a polishing process, the sacrificial oxide layer and the remaining photoresist layer are sequentially eliminated to complete the lower charge storage electrode.
摘要翻译：目的：提供一种用于制造电容器的方法，通过在下电荷存储电极的外壁上形成SiON层来消除电容器之间的桥接问题。构成：在具有用于形成半导体器件的各种元件的半导体衬底（10）上形成层间电介质（12）之后，蚀刻要形成电容器的部分中的层间电介质以形成接触孔。在用于插头的第一多晶硅层（13）埋在接触孔中之后，在整个表面上依次形成牺牲氧化物层，抗反射涂层（ARC）层和光刻胶层图案。进行蚀刻处理以通过使用光致抗蚀剂层图案作为掩模来露出第一多晶硅层。消除光致抗蚀剂层图案以形成由ARC层和牺牲氧化物层组成的图案。在整个表面上施加钝化层之后，对整个表面进行蚀刻处理，直到暴露第一多晶硅层，使得ARC层被去除并且钝化层仅留在牺牲氧化物层图案的一侧。在整个表面上形成用于下电荷存储电极的第二多晶硅层（20），并且掩埋有光致抗蚀剂层。在通过抛光工艺去除光致抗蚀剂层以暴露牺牲氧化物层之后，依次消除牺牲氧化物层和剩余的光致抗蚀剂层以完成下部电荷存储电极。

19. 发明公开

KR1020000043919A 반도체 소자의 정렬 키 형성 방법 无效
标题翻译：形成半导体器件对准方法
公开(公告)号：KR1020000043919A
公开(公告)日：2000-07-15
申请号：KR1019980060357
申请日：1998-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 서윤석 , 이명신
IPC分类号： H01L21/027
摘要： PURPOSE: A method for forming an align key of a semiconductor device is provided to prevent a crack of an insulating layer around the align key pattern. CONSTITUTION: When an align key pattern is formed in a peripheral circuitry region, the align key pattern is subjected to an excessive thermal or mechanical stress in the following thermal process due to a rectangular shape thereof. Therefore, a ring-shaped buffer pattern(D1) is additionally formed around the align key pattern. The ring-shaped buffer pattern(D1) not only isolates the align key pattern from all external influence, but also disperses the stress. Accordingly, the internal stress of the insulating layer may not converge into edges of the align key pattern. The buffer pattern may have a different shape instead of the ring shape. For example, a plurality of circular patterns(D2) enclosing the align key pattern are possible.
摘要翻译：目的：提供一种用于形成半导体器件的对准键的方法，以防止围绕对准键图案的绝缘层的裂纹。构成：当在外围电路区域中形成对准键图形时，由于其矩形形状，对准键图案在随后的热处理中经受过度的热或机械应力。因此，围绕对准键图案另外形成环形缓冲图案（D1）。环形缓冲图案（D1）不仅将对齐键图案与所有外部影响隔离，而且分散应力。因此，绝缘层的内部应力可能不会会聚到对准键图案的边缘。缓冲图案可以具有不同的形状而不是环形。例如，包围对准键图案的多个圆形图案（D2）是可能的。

20. 发明公开

KR1020000027929A 반도체 소자의 제조 방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020000027929A
公开(公告)日：2000-05-15
申请号：KR1019980045974
申请日：1998-10-29
申请人： 에스케이하이닉스 주식회사
发明人： 진승우 , 이명신 , 손용선
IPC分类号： H01L21/28
摘要： PURPOSE: A semiconductor fabrication method is provided to improve a contact resistance between a gate and a bit line by using an RTA(rapid thermal annealing). CONSTITUTION: A gate electrode having a polysilicon layer(20) and a tungsten silicide(25) is formed, and source and drain regions(50) are formed. Then, a first contact hole(70) connected to the gate electrode and a second contact hole(80) connected to the drain region(50) are formed. A bit line(100A) connected to the gate electrode via the first contact hole(70) and a word line(100B) connected to the drain through the second contact hole(80) are formed. For removing an oxide(55) formed at interface connected to the bit and word lines(111A,.100B), an RTA process is performed.
摘要翻译：目的：提供半导体制造方法，通过使用RTA（快速热退火）来提高栅极和位线之间的接触电阻。构成：形成具有多晶硅层（20）和硅化钨（25）的栅电极，形成源区和漏区（50）。然后，形成连接到栅电极的第一接触孔（70）和连接到漏区（50）的第二接触孔（80）。形成了经由第一接触孔（70）连接到栅电极的位线（100A）和通过第二接触孔（80）连接到漏极的字线（100B）。为了除去形成在与位和字线（111A，.100B）连接的接口处的氧化物（55），执行RTA处理。

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