专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

KR1020020017097A 반도체 소자의 커패시터 형성 방법 无效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：KR1020020017097A
公开(公告)日：2002-03-07
申请号：KR1020000050189
申请日：2000-08-28
申请人： 에스케이하이닉스 주식회사
发明人： 이명신 , 임비오
IPC分类号： H01L27/108
摘要： PURPOSE: A method for forming a capacitor of a semiconductor device is provided to simplify manufacturing processes and to prevent the lifting of capacitors generated at edge portions of a wafer by using a thick silicon nitride as an etch stopper. CONSTITUTION: A planarized insulating layer(21) is formed on a semiconductor substrate having cell transistors. After forming a thick nitride layer on the planarized insulating layer(21), contact holes are formed by selectively etching the insulating layer(21) and the thick nitride layer. After sufficiently filling a polysilicon layer into the contact holes, a polysilicon plug(24) is formed by blanket etch-back processing. During the blanket etch-back processing, the thick nitride layer is simultaneously partial etched so as to form a thin silicon nitride layer(22a) while preventing capacitor lifting. Then, a lower electrode(27a) of the capacitor is formed.
摘要翻译：目的：提供一种用于形成半导体器件的电容器的方法，以简化制造工艺，并且通过使用厚氮化硅作为蚀刻停止器来防止在晶片的边缘部分产生的电容器的提升。构成：在具有单元晶体管的半导体衬底上形成平坦化的绝缘层（21）。在平坦化绝缘层（21）上形成厚氮化物层之后，通过选择性地蚀刻绝缘层（21）和厚氮化物层形成接触孔。在将多晶硅层充分地填充到接触孔中之后，通过毯式回蚀处理形成多晶硅插塞（24）。在覆盖层回蚀处理期间，同时对厚氮化物层进行部分蚀刻，以形成薄的氮化硅层（22a），同时防止电容器提升。然后，形成电容器的下电极（27a）。

2. 发明公开

KR1020000043924A 플라즈마 증착 장비 및 이를 이용한 반도체 소자의 절연막형성 방법 无效
标题翻译：等离子体沉积装置和形成半导体器件绝缘膜的方法
公开(公告)号：KR1020000043924A
公开(公告)日：2000-07-15
申请号：KR1019980060362
申请日：1998-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 임비오 , 이승진
IPC分类号： H01L21/31
摘要： PURPOSE: A plasma depositing apparatus is to mount a bias adder between a wafer supporting member and a wafer, which has a plurality of electrodes, thereby forming a thin film having an uniform thickness. CONSTITUTION: A plasma depositing apparatus comprises a chamber(1) which is formed with a gas injecting port(2) and a gas discharging port(3), a wafer supporting member(4) which is mounted at a bottom face of the chamber, a bias adder(5) which is mounted on the wafer supporting member and has a plurality of electrodes formed on a board made of an insulating material, a first high frequency generator(7) for supplying a high-frequency bias voltage to the wafer supporting member and the chamber and a second high frequency generator(8) for supplying a respective different high frequency bias voltage to each electrode of the bias adder. In the apparatus, the electrodes of the bias adder are radially arranged.
摘要翻译：目的：等离子体沉积装置是在晶片支撑构件和晶片之间安装偏置加法器，其具有多个电极，由此形成具有均匀厚度的薄膜。构成：等离子体沉积装置包括形成有气体注入口（2）和气体排出口（3）的腔室（1），安装在腔室的底面的晶片支撑构件（4）偏置加法器（5），其安装在晶片支撑构件上并且具有形成在由绝缘材料制成的板上的多个电极;第一高频发生器（7），用于向晶片支撑提供高频偏置电压以及用于向偏置加法器的每个电极提供各自不同的高频偏置电压的第二高频发生器（8）。在该装置中，偏置加法器的电极被径向布置。

3. 发明公开

KR1020000003516A 필드산화 깊이를 증가 시키기 위한 반도체소자제조방법 无效
标题翻译：半导体器件生产方法来增加氧化物的深度
公开(公告)号：KR1020000003516A
公开(公告)日：2000-01-15
申请号：KR1019980024758
申请日：1998-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 임비오 , 홍택기
IPC分类号： H01L21/31
摘要： PURPOSE: A semiconductor production method is provided to increase a field oxidation in a limited area. CONSTITUTION: The semiconductor is produced in the process of; forming an element separated mask pattern(24) on the semiconductor substrate with an element separated area open; effecting an ion injection to form a channel stop ion injection area(27) in the semiconductor substrate of the above open area injecting as large and heavy ion as may damage the semiconductor substrate, forming a field oxide film by making a field oxidation.
摘要翻译：目的：提供半导体制造方法以增加有限区域的场氧化。规定：半导体生产过程中; 在元件分离区域打开的状态下在半导体衬底上形成元件分离的掩模图案（24）; 进行离子注入，以在上述开放区域的半导体衬底中形成通道停止离子注入区域（27），其注入可能损坏半导体衬底的大而重的离子，通过进行场氧化形成场氧化膜。

4. 发明公开

KR1020020017310A 반도체 소자의 금속 배선 형성 방법 无效
标题翻译：形成金属互连半导体器件的方法
公开(公告)号：KR1020020017310A
公开(公告)日：2002-03-07
申请号：KR1020000050533
申请日：2000-08-29
申请人： 에스케이하이닉스 주식회사
发明人： 임비오 , 이명신
IPC分类号： H01L21/3205
摘要： PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to control stress caused by an intermetallic dielectric(IMD) and an interconnection defect caused by shrinkage of a spin-on-glass(SOG) layer generated in a curing process, by forming a stress buffer layer between a side surface of the metal interconnection and the first IMD. CONSTITUTION: The metal interconnection(32) is formed on a substrate(31). An O2 plasma process is performed regarding the side surface of the metal interconnection to form the stress buffer layer(35) intercepting thermal stress. The first IMD(34) is formed, and an insulation layer(36) for planarization is formed by an SOG coating process. After the second IMD(37) is formed on the insulation layer for planarization, an annealing process is performed to reduce the thermal stress.
摘要翻译：目的：提供一种用于形成半导体器件的金属互连的方法，以控制由金属间电介质（IMD）引起的应力和由固化过程中产生的旋涂玻璃（SOG）层的收缩引起的互连缺陷，通过在金属互连的侧表面和第一IMD之间形成应力缓冲层。构成：金属互连（32）形成在基板（31）上。对金属互连的侧表面进行O2等离子体处理，形成截断热应力的应力缓冲层（35）。形成第一IMD（34），并且通过SOG涂覆工艺形成用于平坦化的绝缘层（36）。在用于平坦化的绝缘层上形成第二IMD（37）之后，进行退火处理以降低热应力。

5. 实用新型

KR2020010001330U 반도체 소자 연마장치의 연마패드 失效
标题翻译：半导体元件抛光装置的抛光垫
公开(公告)号：KR2020010001330U
公开(公告)日：2001-01-15
申请号：KR2019990011732
申请日：1999-06-28
申请人： 에스케이하이닉스 주식회사
发明人： 손기근 , 임비오
IPC分类号： H01L21/304
摘要： 본고안은반도체소자연마장치의연마패드에관한것으로, 웨이퍼의에지부분의연마속도가중앙부의연마속도보다높아연마균일성이저하되고, 슬러리가외부배출되지않아연마장비에결함을일으키는문제점을해결하기위하여, 연마패드주변부의그루브및도를중앙부의그루브밀도보다낮도록하여, 연마막의에지부분에서의연마속도를낮출수 있고, 연마막의전체적인연마도를균일하게할 수있고, 연마패드주변부의그루브를방사형으로설계함에따라슬러리의배출을용이하게할 수있어연마중에발생되는결함을효과적으로감소시킬수 있는반도체소자연마장치의연마패드가개시된다.
摘要翻译：纸建议解决该问题导致了本发明中的缺陷涉及一种半导体装置的抛光垫的抛光装置中，与晶片的边缘部分的抛光速率降低比中央部的研磨速度高的抛光均匀性，这是因为浆料是不放电抛光设备外为了，以便减小槽抛光垫周边比中央部的槽密度的和，该磨料层可以减少eseoui去除速率，抛光层变得均匀整个抛光也是一个边缘，抛光垫周边的径向槽公开了一种半导体元件抛光设备的抛光垫，其能够容易地排出浆料并且有效地减少抛光期间产生的缺陷。

6. 发明公开

KR1020010004709A 반도체 소자의 산화막 형성 방법 无效
标题翻译：形成半导体器件氧化物层的方法
公开(公告)号：KR1020010004709A
公开(公告)日：2001-01-15
申请号：KR1019990025423
申请日：1999-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 임비오 , 이인행
IPC分类号： H01L21/316
摘要： PURPOSE: A method for forming an oxide layer of a semiconductor device is provided to improve the reliability of a device by performing an efficient burying process under a process condition with a high aspect ratio. CONSTITUTION: A method for forming an oxide layer of a semiconductor device comprises the following steps. A lower pattern(12) is formed on an upper portion of a semiconductor substrate(11). An aspect ratio of the lower pattern(12) is more than 4.0. The first oxide layer(13) is formed by using a high density plasma CVD(Chemical Vapor Deposition) method. In the high density plasma CVD method, A deposition ratio is reduced and an etching ratio and an energy are increased by controlling the capacity of a vacuum pump within a chamber.
摘要翻译：目的：提供一种用于形成半导体器件的氧化物层的方法，以通过在具有高纵横比的工艺条件下进行有效的埋入工艺来提高器件的可靠性。构成：用于形成半导体器件的氧化物层的方法包括以下步骤。在半导体衬底（11）的上部形成有下部图案（12）。下图案（12）的长宽比大于4.0。通过使用高密度等离子体CVD（化学气相沉积）法形成第一氧化物层（13）。在高密度等离子体CVD方法中，通过控制室内的真空泵的容量，A沉积比降低，蚀刻比和能量增加。

7. 发明公开

KR1020010004739A 반도체 소자의 저유전 절연막 형성 방법 失效
标题翻译：在半导体器件中形成低介电绝缘膜的方法
公开(公告)号：KR1020010004739A
公开(公告)日：2001-01-15
申请号：KR1019990025453
申请日：1999-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 임비오 , 손기근
IPC分类号： H01L21/31
摘要： PURPOSE: A low dielectric insulating film formation method in semiconductor devices is provided to be capable of minimizing the dielectric constant of an insulating film, by making nitrogen gas within the insulating film trapped of a void shape. CONSTITUTION: A metal line(12) is formed on a semiconductor substrate(11). After the semiconductor substrate(11) is loaded onto the high density plasma deposition equipment, deposition source gas(13) and etch source gas(14) are injected, wherein the etch source gas employs nitrogen gas. Next, an insulating film(15) is deposited by high density plasma, so that nitrogen gas at the insulating film portion is trapped by means of etch source gas(14). Then, a low dielectric insulating film(15) is formed on the semiconductor substrate(11) and the metal line(12).
摘要翻译：目的：提供半导体器件中的低介电绝缘膜形成方法，其能够通过在绝缘膜内捕获空隙形状的氮气使绝缘膜的介电常数最小化。构成：在半导体衬底（11）上形成金属线（12）。在将半导体衬底（11）加载到高密度等离子体沉积设备上之后，注入沉积源气体（13）和蚀刻源气体（14），其中蚀刻源气体采用氮气。接下来，通过高密度等离子体沉积绝缘膜（15），从而通过蚀刻源气体（14）捕获绝缘膜部分处的氮气。然后，在半导体基板（11）和金属线（12）上形成低介电绝缘膜（15）。

8. 发明授权

KR100361203B1 반도체 소자의 저유전 절연막 형성 방법 失效
标题翻译：在半导体器件中形成低电介质膜的方法
公开(公告)号：KR100361203B1
公开(公告)日：2002-11-18
申请号：KR1019990025453
申请日：1999-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 임비오 , 손기근
IPC分类号： H01L21/31
摘要： 본발명은반도체소자의저유전절연막형성방법에관한것으로, 소자의고집적화와고속화에따른전도체간절연막의절연특성을더욱향상시키기위하여, 절연막형성시식각소오스가스로질소가스를이용한고밀도플라즈마를이용하여절연막내에질소가스가보이드형태로트랩되도록하므로써, 절연막의유전율을최소화할수 있는반도체소자의저유전절연막형성방법이개시된다.

9. 发明公开

KR1020000003463A 고집적 반도체 소자의 알루미늄막 형성방법 无效
标题翻译：高密度半导体的铝膜薄膜方法
公开(公告)号：KR1020000003463A
公开(公告)日：2000-01-15
申请号：KR1019980024705
申请日：1998-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 홍택기 , 임비오
IPC分类号： H01L21/3205
摘要： PURPOSE: An aluminum film forming method of a highly integrated semiconductor is provided to improve the reliability and productivity of the element by steadily forming AI membrane of a highly integrated semiconductor. CONSTITUTION: The AI metal wire forming method of a highly integrated semiconductor comprises the steps of: performing the 1st AI sputtering process at a low temperature; the 2nd AI sputtering process at a high temperature; injecting a cooling gas in the same chamber, right after the 2nd AI sputtering process; cooling the AI membrane formed in the process of the 2nd AI sputtering process.
摘要翻译：目的：提供高度集成的半导体的铝膜形成方法，通过稳定地形成高度集成的半导体的AI膜来提高元件的可靠性和生产率。构成：高度集成半导体的AI金属线形成方法包括以下步骤：在低温下进行第一AI溅射工艺; 第二次AI溅射工艺在高温下; 在第二次AI溅射过程之后，在同一个室内注入冷却气体; 冷却在第二次AI溅射工艺过程中形成的AI膜。

10. 实用新型

KR200301077Y1 반도체 소자 연마장치의 연마패드 失效
标题翻译：半导体元件抛光装置的抛光垫
公开(公告)号：KR200301077Y1
公开(公告)日：2003-01-29
申请号：KR2019990011732
申请日：1999-06-28
申请人： 에스케이하이닉스 주식회사
发明人： 손기근 , 임비오
IPC分类号： H01L21/304
摘要： 본 고안은 반도체 소자 연마장치의 연마패드에 관한 것으로, 웨이퍼의 에지 부분의 연마속도가 중앙부의 연마속도보다 높아 연마 균일성이 저하되고, 슬러리가 외부로 배출되지 않아 연마 장비에 결함을 일으키는 문제점을 해결하기 위하여, 연마패드 주변부의 그루브 밀도를 중앙부의 그루브 밀도보다 낮도록 하여, 연마막의 에지부분에서의 연마 속도를 낮출 수 있고, 연마막의 전체적인 연마도를 균일하게 할 수 있고, 연마패드 주변부의 그루브를 방사형으로 설계함에 따라 슬러리의 배출을 용이하게 할 수 있어 연마중에 발생되는 결함을 효과적으로 감소시킬 수 있는 반도체 소자 연마장치의 연마패드가 개시된다.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式