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    • 91. 发明公开
    • 반도체장치의 제조방법
    • 制造半导体器件的方法
    • KR1020040004066A
    • 2004-01-13
    • KR1020030041797
    • 2003-06-26
    • 가부시키가이샤 한도오따이 에네루기 켄큐쇼
    • 모노에시게하루
    • H01L29/786
    • H01L29/78696H01L21/76838H01L29/42384H01L29/4908H01L29/66757H01L29/78621H01L2029/7863
    • PURPOSE: To provide the technology to particularly manufacture, with good reproducibility, TFT having excellent hot carrier resistance by giving a degree of freedom in design to the size of the TFT of the gate overlap LDD structure formed on the self-alignment basis. CONSTITUTION: A gate electrode is formed of a laminated body including a plurality of conductive layers. Widths of a first conductive layer and a second conductive layer in the direction of channel length are set to provide the result that the first conductive layer as the lower layer is longer than the other and the gate electrode is used as the mask for ion-doping to form the LDD. In this case, the optimum shape can be obtained by processing the shape of the mask pattern to form the gate electrode and then combining this process with the dry etching process, in order to set the LDD overlapped with the gate electrode, namely, Lov to 1 μm or more, preferably to 1.5 μm or more.
    • 目的:通过在自对准的基础上形成的栅极重叠LDD结构的TFT的尺寸给予一定程度的设计自由度,提供具有良好再现性的TFT,具有良好的再现性,特别是制造具有优异热载流子电阻的技术。 构成:栅极由包括多个导电层的层叠体形成。 设置沿沟道长度方向的第一导电层和第二导电层的宽度,以提供作为下层的第一导电层比另一个长的结果,并且使用栅电极作为离子掺杂掩模 形成LDD。 在这种情况下,通过处理掩模图案的形状以形成栅电极,然后将该处理与干蚀刻工艺组合,可以获得最佳形状,以便将LDD与栅电极重叠,即Lov到 1μm以上,优选为1.5μm以上。