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1. 发明专利

JP4498633B2 Oscillator circuit, and the internal power supply generating circuit 有权
公开(公告)号：JP4498633B2
公开(公告)日：2010-07-07
申请号：JP2001108748
申请日：2001-04-06
申请人：富士通マイクロエレクトロニクス株式会社
发明人：修一斎藤
IPC分类号： G11C11/407 , H03L5/00 , H02M3/07 , H03K3/03
CPC分类号： H02M3/073

2. 发明专利

JP3891185B2 Receiver circuit, interface circuit, and electronic equipment 有权
公开(公告)号：JP3891185B2
公开(公告)日：2007-03-14
申请号：JP2004065938
申请日：2004-03-09
申请人：セイコーエプソン株式会社
发明人：伸之 ▲斎▼藤 , 幸成柴田 , 卓也石田 , 智良長谷川
IPC分类号： G06F3/00 , H03K19/0175 , H03K19/00 , H03L5/00 , H04B1/16 , H04L25/02 , H04L25/45
CPC分类号： H04L25/45 , H04L25/0292

3. 发明专利

JP2005250664A Voltage regulator 有权
标题翻译：电压稳压器
公开(公告)号：JP2005250664A
公开(公告)日：2005-09-15
申请号：JP2004057714
申请日：2004-03-02
申请人： Oki Electric Ind Co Ltd , Oki Micro Design Co Ltd , 株式会社沖マイクロデザイン , 沖電気工業株式会社
发明人： MATSUSHITA YUICHI
IPC分类号： G05F3/28 , H03L5/00
CPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a voltage regulator for preventing the generation of any large output fluctuation due to overshoot or the like even when a applied power supply voltage is beyond a prescribed input voltage range.
SOLUTION: When a power source potential VCC is lower than a desired DC voltage OUT, the potential of a node N3 of a reference potential adjusting part 50 is made lower than a reference potential REF. Thus, the output of a reference potential generating part 20 is drawn through an NMOS54 to a node N3, and a reference potential REF is decreased to the same potential as a control voltage VC. Thus, a differential amplifying part 30 is turned into a balanced state, and the ON resistance of a PMOS41 of an output part 40 is increased, and currents hardly flows. Therefore, even when the power source potential VCC is rapidly increased to a prescribed voltage, any transient excessive currents can be prevented from flowing through a PMOS 41, and a stable DC voltage OUT can be obtained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使当施加的电源电压超过规定的输入电压范围时，提供一种用于防止由于过冲等产生任何大的输出波动的电压调节器。解决方案：当电源电位VCC低于期望的DC电压OUT时，使参考电位调节部分50的节点N3的电位低于参考电位REF。因此，参考电位产生部分20的输出通过NMOS54被抽取到节点N3，并且参考电位REF被减小到与控制电压VC相同的电位。因此，差分放大部分30变成平衡状态，并且输出部分40的PMOS41的导通电阻增加，并且电流几乎不流动。因此，即使当电源电位VCC迅速增加到规定的电压时，也可以防止任何瞬态过大的电流流过PMOS 41，并且可以获得稳定的DC电压OUT。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005012254A Wireless communication apparatus 审中-公开
标题翻译：无线通信设备
公开(公告)号：JP2005012254A
公开(公告)日：2005-01-13
申请号：JP2003170801
申请日：2003-06-16
申请人： Toshiba Tec Corp , 東芝テック株式会社
发明人： OISHI SADATOSHI , KATO MASAKAZU
IPC分类号： H03L5/00 , H03L7/08 , H03L7/099 , H04B1/40
摘要： PROBLEM TO BE SOLVED: To provide a wireless communication apparatus wherein the CN ratio of a VCO is enhanced and the power consumption of the VCO is reduced. SOLUTION: The wireless communication apparatus, wherein a MIX 16 applies down-conversion to a received signal by using an output signal from a frequency synthesizer 1 provided with the VCO 2, a demodulator 18 demodulates the down-converted received signal, a modulator 20 modulates a baseband signal, and a MIX 22 up-converts the modulated signal and transmits the result, includes: a variable voltage regulator 7 for applying its output voltage to the VCO as a power supply voltage; and a controller 19 for setting a reference voltage from a D/A converter 8 so that the CN ratio of the output signal from the frequency synthesizer satisfies a required CN on the basis of a CN ratio measurement result of the output signal from the frequency synthesizer thereby controlling the output voltage of the variable voltage regulator 7. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种无线通信装置，其中VCO的CN比增强并且VCO的功耗降低。解决方案：无线通信装置，其中MIX16通过使用来自具有VCO2的频率合成器1的输出信号对接收信号进行下变频，解调器18对下变频接收信号进行解调，调制器20调制基带信号，并且MIX22上变频调制信号并发送结果，包括：可变电压调节器7，用于将其输出电压施加到VCO作为电源电压; 以及控制器19，用于根据来自频率合成器的输出信号的CN比测量结果，设置来自D / A转换器8的参考电压，使得来自频率合成器的输出信号的CN比满足所需的CN 从而控制可变电压调节器7的输出电压。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004349830A Level shift circuit 有权
标题翻译：水平移位电路
公开(公告)号：JP2004349830A
公开(公告)日：2004-12-09
申请号：JP2003142160
申请日：2003-05-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MOCHIZUKI KOJI
IPC分类号： H03M1/74 , H03F3/45 , H03K5/08 , H03L5/00 , H03M1/10 , H03M1/66 , H03M1/70
CPC分类号： H03F3/45475 , H03F3/45941 , H03F3/45959 , H03F2203/45212 , H03F2203/45588
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit with a sophisticated function and high accuracy without being affected by an offset error of operational amplifiers and by an output dynamic range of a digital / analog converter being a signal source.
SOLUTION: This circuit is provided with: two resistors 4o an 4p whose resistance equal to each other connected between differential output terminals; and an operational amplifier 4r for carrying out level shift control, thus the circuit performs a feedback operation so that each average voltage of differential outputs 4i, 4m is always matched with a DC reference level 4q independently of the offset error of the operational amplifiers to realize a level shift function with less error. Further, series connection of resistors 4h, 4l between the level shift circuit and a differential output of a digital / analog converter 4a attains a voltage output at the outside of an output dynamic range of the digital / analog converter 4a.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有复杂功能和高精度的电平移位电路，而不受运算放大器的偏移误差和作为信号源的数字/模拟转换器的输出动态范围的影响。
解决方案：该电路设有：两个电阻器4o和4p，其电阻彼此相差连接在差分输出端子之间; 以及用于执行电平移位控制的运算放大器4r，因此电路执行反馈操作，使得差分输出4i，4m的每个平均电压总是与直流参考电平4q匹配，而与运算放大器的偏移误差无关，以实现具有较小误差的电平移位功能。此外，电平移位电路和数/模转换器4a的差分输出之间的电阻器4h，41的串联连接在数/模转换器4a的输出动态范围的外部获得电压输出。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004266662A Device and method for offset voltage correction 有权
公开(公告)号：JP2004266662A
公开(公告)日：2004-09-24
申请号：JP2003056197
申请日：2003-03-03
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： KINUGASA YUKIHISA
IPC分类号： H03K5/08 , H03F3/34 , H03K5/24 , H03L5/00
CPC分类号： H03K5/2481 , H03K5/249
摘要： PROBLEM TO BE SOLVED: To provide a device and a method for offset voltage correction capable of correcting the input offset voltage of a comparator circuit with very high accuracy. SOLUTION: When the input offset voltage of a comparator CMP is detected, a counter circuit 12 conducts both up-counting and down-counting operations of a clock signal CLK. An offset voltage correcting circuit 14 obtains the value (counter value CVu) of a counter signal Sc corresponding to an input offset voltage when a comparison signal Scmp changes from "1" to "0" and a value (counter value CVd) of the counter signal Sc corresponding to the input offset voltage when the comparison signal Scmp changes from "0" to "1". The offset voltage correcting circuit 14 conducts a predetermined computation using the counter values CVu and CVd. The offset voltage of the comparator CMP is corrected based on the result of the computation. COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2004236164A Level conversion circuit with automatic delay adjustment function 有权
公开(公告)号：JP2004236164A
公开(公告)日：2004-08-19
申请号：JP2003024449
申请日：2003-01-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ITO YOSHIKAZU , NAKANISHI KAZUYUKI , YAMAMOTO HIROO , HIRATA AKIO , HATSUDA TSUGUYASU
IPC分类号： H03K19/0185 , H03K3/011 , H03K3/356 , H03K5/153 , H03L5/00
CPC分类号： H03K3/356113 , H03K3/011
摘要： PROBLEM TO BE SOLVED: To keep a good balance between a fall delay time characteristic and a rise delay time characteristic of an output signal even when at least one of amplitude voltages of an input signal and the output signal is changed in a level conversion circuit.
SOLUTION: When an amplitude voltage (first power supply voltage VDDL) of an input signal of an input terminal in is changed to a high voltage, and an amplitude voltage (second power supply voltage VDDH) of an output signal of an output terminal out is changed to a low voltage, a fall delay time of the signal from the output terminal out easily becomes longer than a rise delay time. However, since an inversion input signal through an inverter I1 is inputted to a level conversion portion L and to a gate of an N type transistor N3, the N type transistor N3 is turned ON when the input signal of the input terminal in falls, current is supplied to an output node n3 of the level conversion portion L from the second power supply voltage DDDH, and a conversion to an H level at the level conversion portion L is assisted.
COPYRIGHT: (C)2004,JPO&NCIPI

8. 发明专利

JP2002305441A METHOD FOR CONTROLLING OSCILLATOR CIRCUIT, OSCILLATOR CIRCUIT, METHOD FOR CONTROLLING INTERNAL POWER SUPPLY GENERATING CIRCUIT, AND THE INTERNAL POWER SUPPLY GENERATING CIRCUIT 失效
公开(公告)号：JP2002305441A
公开(公告)日：2002-10-18
申请号：JP2001108748
申请日：2001-04-06
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： SAITO SHUICHI
IPC分类号： G11C11/407 , H02M3/07 , H03K3/03 , H03L5/00
摘要： PROBLEM TO BE SOLVED: To provide a method for controlling an oscillator circuit, in which internal power can be supplied stably and efficiently, and to provide an oscillator circuit, a method for controlling an internal power supply generating circuit, and an internal power supply generating circuit. SOLUTION: An abnormal pulse preventive circuit 14 comprises a pulse generating circuit 31, a combiner 32, and a first oscillator circuit 33, where the first oscillator circuit 33 comprises a period circuit 43 comprising a period delay circuit 41 and a switching circuit 42, and a switch control circuit 44. At active time, the first oscillator circuit 33 outputs an oscillator signal OSC, having a first frequency based on a detection signal DET-A inputted to the combiner 32. At standby, the first oscillator circuit 33 oscillates at the same period as that of the second frequency (first frequency > second frequency) of an oscillator signal OSC-S from a second oscillator circuit 15 being inputted via the pulse generating circuit 31.

9. 发明专利

JP3327911B2 失效
公开(公告)号：JP3327911B2
公开(公告)日：2002-09-24
申请号：JP2001181082
申请日：2001-06-15
IPC分类号： H03B5/32 , H03B5/38 , H03L5/00

10. 发明专利

JP3218250B2 失效
公开(公告)号：JP3218250B2
公开(公告)日：2001-10-15
申请号：JP22814991
申请日：1991-05-30
IPC分类号： H03B5/32 , H03B5/38 , H03L5/00

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