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1. 发明专利

JP2008099517A Information processing device, communications device, information reproducing device, image display device, electronic device, electronic control device, and moving body 审中-公开
标题翻译：信息处理设备，通信设备，信息再现设备，图像显示设备，电子设备，电子控制设备和移动体
公开(公告)号：JP2008099517A
公开(公告)日：2008-04-24
申请号：JP2006281259
申请日：2006-10-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMAMOTO HIROO
IPC分类号： H02J1/00 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide an information processing device consisting of a plurality of electrical circuit elements for general-purpose current reuse. SOLUTION: The information processing device comprises a connection switching device which couples and connects electric circuit elements so that the operating current amounts are equal, among a plurality of electrical circuit elements. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供由用于通用电流再利用的多个电路元件组成的信息处理装置。解决方案：信息处理装置包括在多个电路元件之间耦合并连接电路元件使得工作电流量相等的连接开关装置。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004257815A Inspection method of semiconductor integrated circuit and semiconductor integrated circuit device 审中-公开
公开(公告)号：JP2004257815A
公开(公告)日：2004-09-16
申请号：JP2003047484
申请日：2003-02-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUMAMARU TOMOYUKI , YAMAMOTO HIROO
IPC分类号： G01R31/26 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method for failure analysis of a semiconductor integrated circuit enabling an IDDQ test even in a greatly miniaturized process.
SOLUTION: An LSI 1 is equipped with a signal input/output terminal 2, a power source potential supply terminal 3, a ground potential supply terminal 4, a substrate potential supply terminal 5 of an Nch transistor, and a substrate potential supply terminal 6 of a Pch transistor. The LSI 1 is inspected by an external current inspection circuit 200 at the IDDQ test time. A determination result on whether a value determined by subtracting the current flowing in substrate potential supply wiring 9 of the Pch transistor and in substrate potential supply wiring 10 of the Nch transistor from the current flowing in power source potential supply wiring 7 is higher or lower than a prescribed determination standard current value recorded in the power source current inspection circuit 200 is outputted by an inspection determination signal.
COPYRIGHT: (C)2004,JPO&NCIPI

3. 发明专利

JP2004236164A Level conversion circuit with automatic delay adjustment function 有权
公开(公告)号：JP2004236164A
公开(公告)日：2004-08-19
申请号：JP2003024449
申请日：2003-01-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ITO YOSHIKAZU , NAKANISHI KAZUYUKI , YAMAMOTO HIROO , HIRATA AKIO , HATSUDA TSUGUYASU
IPC分类号： H03K19/0185 , H03K3/011 , H03K3/356 , H03K5/153 , H03L5/00
CPC分类号： H03K3/356113 , H03K3/011
摘要： PROBLEM TO BE SOLVED: To keep a good balance between a fall delay time characteristic and a rise delay time characteristic of an output signal even when at least one of amplitude voltages of an input signal and the output signal is changed in a level conversion circuit.
SOLUTION: When an amplitude voltage (first power supply voltage VDDL) of an input signal of an input terminal in is changed to a high voltage, and an amplitude voltage (second power supply voltage VDDH) of an output signal of an output terminal out is changed to a low voltage, a fall delay time of the signal from the output terminal out easily becomes longer than a rise delay time. However, since an inversion input signal through an inverter I1 is inputted to a level conversion portion L and to a gate of an N type transistor N3, the N type transistor N3 is turned ON when the input signal of the input terminal in falls, current is supplied to an output node n3 of the level conversion portion L from the second power supply voltage DDDH, and a conversion to an H level at the level conversion portion L is assisted.
COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2008067411A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008067411A
公开(公告)日：2008-03-21
申请号：JP2007293520
申请日：2007-11-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMAMOTO HIROO , SAKIYAMA SHIRO
IPC分类号： H03K19/00 , H01L21/822 , H01L27/04 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing an increase of a layout area caused by laying around power supply wiring in a case where a plurality of power sources are included within a logic block. SOLUTION: A plurality of logic circuits operating with an equal power supply voltage are disposed together as a common power supply logic circuit block 122 and around the common power supply logic circuit block 122, logic circuit blocks 103, 104 operating with a power supply voltage different from that of the common power supply logic circuit block 122 are disposed with a level shifter circuit block 131 with a level shifter circuit formed therein inbetween. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其能够抑制在逻辑块内包含多个电源的情况下由敷设在电源布线周围引起的布局区域的增加。解决方案：以等电源电压工作的多个逻辑电路一起设置为公共电源逻辑电路块122，并围绕公共电源逻辑电路块122，逻辑电路块103,104以功率运行与公共电源逻辑电路块122不同的电源电压设置有电平移位器电路块131，其间形成有电平移位电路。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2004349681A Semiconductor device and design method therefor 有权
公开(公告)号：JP2004349681A
公开(公告)日：2004-12-09
申请号：JP2004085027
申请日：2004-03-23
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KATSURA AKIHITO , YAMAMOTO HIROO
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To suppress reduction of a degree of circuit integration by the enlargement of the interval of signal lines, and by inserting a shield line or a shielding layer between the signal lines, and to prevent malfunctions of the circuit due to noise.
SOLUTION: The device has a multilayer wiring structure, in which three or more wiring layers are stacked on a silicon semiconductor substrate, and is equipped with a first signal line 12 which is formed by a (N-1)-th wiring layer, and constitutes a latch circuit, a second signal line 13 which has a part arranged being crossed or overlapped partially the first signal line 12, and formed by a (N+1)-th wiring layer, and a power line 14 which is formed by a N-th wiring layer between the first signal line 12 and the second signal line 13, and on the just lower portion of the second signal line 13, and functions as a shield wiring. The noise generated by voltage fluctuation of the second signal line 13 is shielded with the power line 14, and the malfunction of the latch circuit can be prevented; and a shield wiring need not be provided separately from the power line 14.
COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2003046087A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2003046087A
公开(公告)日：2003-02-14
申请号：JP2001231353
申请日：2001-07-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIRATA AKIO , YAMAMOTO HIROO
IPC分类号： H01L27/112 , H01L21/8244 , H01L21/8246 , H01L27/11 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, having improved operating speed and reliability by suppressing increase in the area and fixing the body potential of a MOSFET in the semiconductor integrated circuit.
SOLUTION: The semiconductor integrated circuit comprises a plurality of MOSFETs, each formed on an SOI substrate and consisting of a gate electrode 1 formed on a substrate, a source and drain region 2 containing n-type impurity, and a body region containing p-type impurity formed below the gate electrode in the substrate; a body contact 8; a low-concentration p-type region 6 interposed between the body regions of the MOSFETs; and a connection region 7 interposed between the low-concentration p-type region 6 and the body contact 8 in the substrate. Since the body region 9 is connected to the body contact 8, its potential is fixed, and the operating speed is increased. Moreover, since one body contact is formed with respect to the plurality of body regions, increase in area can be prevented.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种半导体集成电路，其通过抑制半导体集成电路中的MOSFET的面积增加和体电位固定而提高了工作速度和可靠性。解决方案：半导体集成电路包括多个MOSFET，每个MOSFET形成在SOI衬底上，由形成在衬底上的栅电极1，含有n型杂质的源极和漏极区域2以及包含p型形成在基板的栅电极下方的杂质; 身体接触8; 介于MOSFET的体区之间的低浓度p型区域6; 以及插入在基板中的低浓度p型区域6和体接触部8之间的连接区域7。由于身体区域9与身体接触部8连接，其电位固定，操作速度增加。此外，由于相对于多个身体区域形成一体接触，因此可以防止面积的增加。

7. 发明专利

JP2005100450A Cell library database and design support system 审中-公开
标题翻译：细胞库数据库和设计支持系统
公开(公告)号：JP2005100450A
公开(公告)日：2005-04-14
申请号：JP2004323988
申请日：2004-11-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MORIWAKI TOSHIYUKI , SAKIYAMA SHIRO , YAMAMOTO HIROO , KAJIWARA JUN , KINOSHITA MASAYOSHI
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a cell library database and a design support system which can perform logic simulation the whole logical unit in a lump, even about a logical unit that has the control function of the supply and the stoppage of deliveries of power.
SOLUTION: In the cell library database, a standard cell is equipped with one or more power source terminals as logic terminals, and function information of the standard cell of each item in the cell library database 13 includes logic information or delay information to the output terminals of one or more power source terminals respectively; a macro cell is equipped with one or more power source terminals as logic terminals, and function information of the macro cell of each item in the cell library database 13 includes logic information or delay information to the output terminals of one or more power source terminals respectively; and the design support system performs logic simulation etc. using the cell library database 13.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一个单元库数据库和一个设计支持系统，可以对整个逻辑单元进行逻辑仿真，即使是具有供应和停止传送控制功能的逻辑单元的权力。解决方案：在单元库数据库中，标准单元配备有一个或多个电源端子作为逻辑端子，并且单元库数据库13中每个项目的标准单元的功能信息包括逻辑信息或延迟信息一个或多个电源端子的输出端子; 宏单元配备有一个或多个电源端子作为逻辑端子，并且单元库数据库13中的每个项目的宏单元的功能信息分别包括一个或多个电源端子的输出端子的逻辑信息或延迟信息 ; 并且设计支持系统使用单元库数据库13来执行逻辑模拟等等。（C）版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2003092350A SEMICONDUCTOR INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY 审中-公开
公开(公告)号：JP2003092350A
公开(公告)日：2003-03-28
申请号：JP2001281433
申请日：2001-09-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIRATA AKIO , YAMAMOTO HIROO , KATSURA AKIHITO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To make the power supply voltage drop small when a semiconductor integrated circuit operates, and layout correction minimum when a repeater is inserted to shorten TAT. SOLUTION: The circuit is provided with function cell areas 9a and 9b for constituting a logic function and auxiliary cell areas 10a to 10c for inserting the repeater into power supply capacity and long distance wiring. A first cell library group 8 for realizing the logic function of the semiconductor integrated circuit and a second cell library group 13 for constituting the function of power supply capacity 5 or an inversion buffer 6 or a buffer 7 are installed as a standard cell library 14. First standard cells 1a to 1f constituted of the elements of the first cell library group 8 are arranged and wired in the function cell areas 9a and 9b. Second standard cells 2a to 2f constituted of the elements of the second cell library group 13 are arranged and wired in the auxiliary cell areas 10a to 10c.

9. 发明专利

JP2002353799A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS DRIVE METHOD 失效
公开(公告)号：JP2002353799A
公开(公告)日：2002-12-06
申请号：JP2001152858
申请日：2001-05-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIRATA AKIO , YAMAMOTO HIROO
IPC分类号： G06F1/04 , H03K19/003
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that prevents malfunction and is operated at a high-speed even when the operating characteristics of the circuit are changed and to provide its drive method. SOLUTION: The semiconductor integrated circuit is provided with a flip-flop 14a, a combination logic circuit 16a, a combination logic circuit 16v, a clock signal generating circuit 20 and a malfunction detection circuit 15a, and the clock signal generating circuit 20 has a mechanism of generating a check signal Sch. The malfunction detection circuit 15a compares an input signal Sin1 to the flip-flop 14a with an output signal Sou1 from the flip-flop 14a, generates a malfunction signal Ser1 when the both differ from each other and delays the clock signal by one clock period. Thus, the malfunction of semiconductor integrated circuit is prevented and high-speed operations can be realized.

10. 发明专利

JP2001196588A SOI STRUCTURE MOS SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001196588A
公开(公告)日：2001-07-19
申请号：JP2000000621
申请日：2000-01-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KATSURA AKIHITO , YAMAMOTO HIROO
IPC分类号： H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a MOS semiconductor device of SOI structure which reduces contact resistance and contact parasitic capacitance and its layout, which dose not require high accuracy of a mask alignment. SOLUTION: A MOS semiconductor device is composed of a first conductivity first semiconductor region 1 which is completely isolated from its surroundings and formed on an insulating layer, a gate electrode 2 formed in the first semiconductor region 1 bestriding it through the intermediary of a gate insulating film, a source region 3 and a drain region 4, which are both doped with second conductivity impurities and formed coming into contact with a body region under the gate electrode 2, and furthermore the MOS semiconductor device is provided with a body contact region 5, which is formed by injecting first conductivity impurities into a region of the semiconductor region 1, in which the source 3 and drain region 4 are not provided from a point kept in contact with the body region 9 under the gate electrode on the extension line of the gate electrode 2 toward its own source electrode, where the body contact region 5 is connected to the self-source electrode 6, in a U-shape.

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