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1. 发明专利

JPH06103490B2 失效
公开(公告)号：JPH06103490B2
公开(公告)日：1994-12-14
申请号：JP16507985
申请日：1985-07-26
IPC分类号： G06F17/10 , G06F15/31

2. 发明专利

JPH06301710A METHOD AND DEVICE FOR DOUBLE PRECISION PRODUCT-SUM OPERATION 失效
公开(公告)号：JPH06301710A
公开(公告)日：1994-10-28
申请号：JP8768293
申请日：1993-04-15
申请人： FUJITSU LTD
发明人： CHIN HON
IPC分类号： G06F17/10 , G06F15/31
摘要： PURPOSE:To shorten the number of cycles of the product-sum operation of a specific value or below by adding the accumulation of the middle partial product to the accumulation of the lower partial product and the accumulation of the upper partial product. CONSTITUTION:A middle accumulator accM of 40-bit width for accumulating singly the partial product of the upper digit and the lower digit of unit word length data is provided as an accumulator for holding the accumulation of a result of multiplication. Also, this device is provided with a bit shifter BS2 for outputting data M held by this middle accumulator accM as data obtained by shifting it by 16 bits to the higher rank is accordance with a command, the M being as it is, or data obtained by shifting it by 16 bits to the lower direction. In such a way, three processings of a data transfer to a multiplier input register, multiplication for deriving the partial product, and an operation for adding the derived partial product to a result of accumulation on the corresponding accumulator are executed in four cycles, respectively. Accordingly, a processing cycle of a double precision product-sum operation which requires six cycles up to the present can be shortened to four cycles and an arithmetic processing can be executed at a high speed.

3. 发明专利

JPH06246064A ADDITIONAL EQUIPMENT FOR TV GAME MACHINE 失效
公开(公告)号：JPH06246064A
公开(公告)日：1994-09-06
申请号：JP5785093
申请日：1993-02-23
申请人： VICTOR COMPANY OF JAPAN
发明人： TANAKA YOSHIAKI
IPC分类号： H04S1/00 , A63F13/25 , A63F13/54 , G06F17/10 , H04S5/00 , H04S7/00 , A63F9/22 , G06F15/31
摘要： PURPOSE:To provide additional equipment (audio-and video-converting cartridge) for a TV game machine, which is used for incorporating a sound and/image normal position control device. CONSTITUTION:A data bus 10 connected to a central processing unit 31 communicates with the inside of a sound and image converting cartridge 1 incorporated with an interface (IF) 7 which is connected with an additional center processing unit (SUB, CPU) 5 in the sound and image converting cartridge 1, an additional sound source 6, and a sound and image converter 8 having convolvers 8a, 8b for carrying out convoluting computation for left and right sound voice signals through the intermediary of an internal bus 11 in the cartridge 1.

4. 发明专利

JPH06231287A METHOD AND DEVICE FOR GENERATING CHAOS SIGNAL 失效
公开(公告)号：JPH06231287A
公开(公告)日：1994-08-19
申请号：JP3954793
申请日：1993-02-03
申请人： NEW JAPAN RADIO CO LTD , YAMAKAWA RETSU
发明人： KITAMURA MASAYOSHI , YAMAKAWA RETSU
IPC分类号： G06G7/26 , G06F17/10 , H03H17/00 , H03H17/02 , G06F15/31
摘要： PURPOSE:To provide the method and device for generating chaos signals. CONSTITUTION:The output of a delay element 10 at the forefront stage from among delay elements 10-14 connected in series is given to a non-linear function element 30 and the output of other delay elements 11-14 is given to coefficient elements 41-44. The non-linear function element 30 and the coefficient elements 41-44 are added by an addition element 50. The addition result is returned to the delay element 10 at the forefront stage. The operation starts by giving the initial value in a batch from initializing elements 20-24. The delay, non-linear operation, coefficient multiplication and addition are executed repeatedly at the proper time cycle DELTAt. During the while, the non-linear function of the non- linear function element is switched by the signal binarizing the external input signal.

5. 发明专利

JPH06214761A METHOD AND CIRCUIT FOR GENERATING PARTIAL PRODUCT 失效
公开(公告)号：JPH06214761A
公开(公告)日：1994-08-05
申请号：JP689993
申请日：1993-01-19
申请人： SONY CORP
发明人： OKI MITSUHARU
IPC分类号： G06F7/533 , G06F7/52 , G06F17/10 , G06F15/31
摘要： PURPOSE:To reduce a circuit scale compared to a conventional one even if the range of a multiplier is slightly larger than a prescribed range. CONSTITUTION:D2=-A5X2+A4+A3, D1=-A3X2+A2+A1 and D0=-A1X2+A0 are obtained by three booth decoders. When A6=0, A5=1 and A4=0 in a selector 50 following the decoders, it is compulsorily set to be D2=+2, and it is compulsorily set to be D2=-2 when A6=1, A5=0 and A4=1. Namely, the selector 50 selects a X2 signal when a signal (a) is high and the selector 50 selects a X(-2) signal when a signal (b) is high. The output of the decoder is selected except this cases. A partial product is calculated by the outputs.

6. 发明专利

JPH06202679A SOUND FIELD CONTROL PROCESSING CIRCUIT 失效
公开(公告)号：JPH06202679A
公开(公告)日：1994-07-22
申请号：JP35956692
申请日：1992-12-25
申请人： FUNAI DENKI KENKYUSHO KK
发明人： TAKAHASHI TORU
IPC分类号： G10K15/12 , G06F17/10 , G11B20/10 , H03H17/00 , H03H17/02 , H03H21/00 , H04B14/04 , G06F15/31
摘要： PURPOSE:To perform highly precise sound field control through a small number of filters by compressing a sound field coefficient based upon a sound field impulse response adaptively to PASC and decreasing the number of parameter setting points, and performing a convolutional process for a PASC signal by a variable bit accumulator. CONSTITUTION:The PASC signal reproduced by a reproducing head from a digital audio cassette tape is applied to the variable bit accumulator 1 after 10-8 demodulation. A sound field control coefficient storage part 3, on the other hand, is stored with sound field control coefficients of parameters compressed corresponding to PASC. For the compressed sound field control coefficients, the PASC signal is convolutionally processed by the variable bit accumulator 1 under the control of a control part 4, but the timing is controlled by the control part 4. The PASC signal to which a sound field signal is added is decoded by a decoder 2 into a digital audio signal, which is reproduced by DAC, thereby obtaining a reproduced sound having desired sound field effect.

7. 发明专利

JPH06189399A ACOUSTIC SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH06189399A
公开(公告)日：1994-07-08
申请号：JP35635992
申请日：1992-12-21
申请人： VICTOR COMPANY OF JAPAN
发明人： FUCHIGAMI NORIHIKO , NAKAYAMA MASAHIRO
IPC分类号： G10K15/00 , G06F17/10 , H03G5/16 , H04R1/40 , H04S1/00 , G06F15/31
摘要： PURPOSE:To obtain the acoustic signal processing unit capable of reproducing a stereoscopic sound only with a speaker installed in front. CONSTITUTION:An acoustic signal processing unit 1 shown in figure A uses signal processing circuits 13a, 13b to apply convolution operation processing to signals S1, S2 to be subjected to spatial sound image localization processing thereby generating spatial sound image localization signals l1, r1, l2, r2 and they are added into stereo signals L, R and they are reproduced from a couple of speakers sp1, sp2 located in front of a listener, Thus, the processing is performed so as to localize a sound image to a spatial position intended by each spatial localizing signal. As a result, the sound image localized in the rear of the listener M and a sound field shown in dotted lines in figure (A) spread up to the rear of the listener M are expressed by using only a couple of the speakers sp1, sp2 arranged in front.

8. 发明专利

JPH06152330A DIGITAL FILTER 失效
公开(公告)号：JPH06152330A
公开(公告)日：1994-05-31
申请号：JP30209192
申请日：1992-11-12
申请人： NEC CORP
发明人： SAKURAI AKINORI
IPC分类号： H03H7/00 , G06F17/10 , G06T5/20 , H03H17/02 , H03H17/06 , G06F15/31 , G06F15/68
摘要： PURPOSE:To execute much calculation within a fixed time and to improve the order of filters by providing a digital filter with a switching function for switching the upper and lower bits of an accumulator and a timing generating circuit for generating the timing of the switching function. CONSTITUTION:The digital filter having 16 bits for data and 16 bits for coefficients, for example, is provided with a RAM 1 having 16-bit width, 16-bit register 2 for storing data for a fixed time, an 8-bit width ROM 3 for storing the coefficient of a filter, an 8-bit register 4 for storing data for a fixed time, and a multiplier 5 consisting of 16 bits X 8 bits. The input/output of an accumulator show whether the lower 25 bits of the accumulator are to be selected or upper 8 to 32 bits are to be selected and show whether the output of an adder 7 is to be inputted to the lower 24 bits or upper 8 to 32 bits of the accumulator 9 in a switching circuit 8. When all upper bits are '0' or '1', processing can be completed only by one multiplication.

9. 发明专利

JPH06139354A HIGH SPEED HISTOGRAM GENERATOR 失效
公开(公告)号：JPH06139354A
公开(公告)日：1994-05-20
申请号：JP13811892
申请日：1992-05-29
申请人： NEC CORP
发明人： ADACHI TADASHI
IPC分类号： H04N1/407 , G06F17/10 , G06T1/20 , G06T7/00 , H04N1/40 , G06F15/70 , G06F15/31
摘要： PURPOSE:To generate a histogram with a simple constitution at high speed when the histogram of input digital image data is generated. CONSTITUTION:When memories 5 that histogram blocks (1) 8 and (2) 9 have are made to generate the histograms of N-bit numerical data alternately and the histograms are read at last, the reading is performed while adding the contents of the two memories 5 by an adder 13. A timing generator 11 sets the timing necessary for the histogram generation and an address generation circuit 3 generates an address signal that a selector 4 selects either one of the output of the address latch circuit 2 as the address of the memory 5. A reset circuit 10 performs the zero clear of a data latch circuit 1. The output of the data latch circuit 7 is written as the input of the memory 5, reading data is added by +1 by an increment device 6 and is supplied to the data latch circuit 7, and the histograms are alternately generated within the two memories 5.

10. 发明专利

JPH06131160A SUM OF PRODUCTS ARITHMETIC CIRCUIT 失效
公开(公告)号：JPH06131160A
公开(公告)日：1994-05-13
申请号：JP30443392
申请日：1992-10-19
申请人： OLYMPUS OPTICAL CO
发明人： ISHII MICHIO
IPC分类号： G06F7/50 , G06F7/52 , G06F7/523 , G06F7/53 , G06F17/10 , G06F15/31
摘要： PURPOSE:To provide a sum of products arithmetic circuit capable of executing sum of products operation at high speed through simple configuration. CONSTITUTION:A high-speed sum of products arithmetic circuit is constituted without using a built-on addition circuit by bit-weighting and impressing an augend in the sum of products operation to the terminal of a unit circuit U00, U01, U11, U21 clamped to a GND among the unit circuits b00 to U21 to calculate the sum of partial products of a multiplication circuit.

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