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1. 发明专利

JP4959913B2 Magnetoresistive memory element and a method of manufacturing the same 有权
公开(公告)号：JP4959913B2
公开(公告)日：2012-06-27
申请号：JP2003313271
申请日：2003-09-04
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：亨俊金
IPC分类号： H01F10/20 , H01L27/105 , G11C11/00 , G11C11/15 , G11C11/16 , H01F41/14 , H01L21/8246 , H01L27/22 , H01L29/76 , H01L29/82 , H01L43/08 , H01L43/12
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/16 , H01L43/08 , H01L43/12 , Y10S257/90 , Y10T29/49021

2. 发明专利

JP4744576B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4744576B2
公开(公告)日：2011-08-10
申请号：JP2008232571
申请日：2008-09-10
申请人：パナソニック株式会社
发明人：政幸亀井 , 恭司山下 , 大策生駒
IPC分类号： H01L21/336 , H01L21/28 , H01L21/768 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/28202 , H01L21/76897 , H01L29/41775 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , Y10S257/90

3. 发明专利

JPWO2008114341A1 半導体装置およびその製造方法有权
公开(公告)号：JPWO2008114341A1
公开(公告)日：2010-06-24
申请号：JP2009504941
申请日：2007-03-16
申请人：富士通マイクロエレクトロニクス株式会社
发明人：奥野　昌樹 , 昌樹奥野
IPC分类号： H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11
CPC分类号： H01L29/78 , H01L21/32139 , H01L21/823468 , H01L27/0203 , H01L27/11 , Y10S257/90 , Y10S257/903
摘要：半導体装置の製造方法は、半導体基板上にゲート電極材料膜を成膜し、前記ゲート電極材料膜を線状にパタニングし、前記線状のゲート電極材料膜パタンの長辺に沿ってサイドウォールを形成し、その後に、前記直線を所定の箇所で切断して、複数のゲート電極に分断する工程を含む。

4. 发明专利

JP2008515240A Gate stack 审中-公开
公开(公告)号：JP2008515240A
公开(公告)日：2008-05-08
申请号：JP2007534850
申请日：2005-09-30
申请人：インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人：シャンク、スティーブン、エム , タッカー、デボラ、エー , トリプレット、マイケル、シー , マーティン、デール、ダブリュー
IPC分类号： H01L29/78 , H01L21/28 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要：【課題】上部領域が破損しにくいゲート・スタックを提供する。
【解決手段】半導体基板（１１０）においてソース／ドレイン領域を定めるのに用いられるゲート・スタック構造体及びその製造方法である。本方法は、（ａ）基板（１１０）の上にゲート誘電体層（１２０）を形成し、（ｂ）ゲート誘電体層（１２０）の上にゲート・ポリシリコン層（１３０）を形成し、（ｃ）ゲート・ポリシリコン層（１３０）の上部層（１３０ａ）にｎ型ドーパントを注入し、（ｄ）基板（１１０）の上にゲート・スタック（１３２、１３４、１２２）を形成するように、ゲート・ポリシリコン層（１３０）及びゲート誘電体層（１２０）の一部をエッチングによって除去し、（ｅ）窒素運搬ガスの存在下でゲート・スタック（１３２、１３４、１２２）の側壁を熱酸化することを含む。結果として、拡散バリア層（１７０）が、ドープ濃度に関わらずゲート・スタック（１３２、１３４、１２２）のポリシリコン材料内の同じ深さのところに形成される。したがって、ゲート・スタックのｎ型ドープ領域（１３２）は、ゲート・スタック（１３２、１３４、１２２）の非ドープ領域（１３４）の幅と等しい幅を有する。
【選択図】図６

5. 发明专利

JP2008098567A Nonvolatile semiconductor memory, and its manufacturing method 审中-公开
标题翻译：非线性半导体存储器及其制造方法
公开(公告)号：JP2008098567A
公开(公告)日：2008-04-24
申请号：JP2006281522
申请日：2006-10-16
申请人： Toshiba Corp , 株式会社東芝
发明人： KAJIMOTO SANETOSHI
IPC分类号： H01L21/8234 , H01L21/768 , H01L21/8247 , H01L23/522 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S257/90
摘要： PROBLEM TO BE SOLVED: To prevent deterioration of reliability caused by the direct contact of a silicon nitride film with the surface of the source/drain region of a high breakdown voltage transistor of a peripheral circuit region, with the composition forming the silicon nitride film in a memory cell region.
SOLUTION: In a silicon substrate 1, a gate insulating film 4b, a polycrystalline silicon film 5, an electrode insulating film 6, and a polycrystalline silicon film 7 are laminated, and then a gate electrode GHV is formed by etching. Ion implantation is performed after removing the gate insulating film 4b on a source/drain region 1d. After a spacer 10a is formed in the side wall of the gate electrode GHV, a silicon oxide film 11 and a silicon nitride film 12 are formed in the surface of the spacer 10a and the surface of the silicon substrate 1, and a silicone oxide film 13 is formed and made flat thereon. Since the silicon nitride film 12 is not directly contacted on the surface of the source/drain region 1d of the high breakdown voltage transistor, the ingress of a hot carrier or the like is prevented, thus improving reliability.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止氮化硅膜与外围电路区域的高击穿电压晶体管的源极/漏极区域的表面的直接接触引起的可靠性的劣化，其中组成形成硅存储单元区域中的氮化物膜。解决方案：在硅衬底1中，层叠栅极绝缘膜4b，多晶硅膜5，电极绝缘膜6和多晶硅膜7，然后通过蚀刻形成栅电极GHV。在去除源极/漏极区域1d上的栅极绝缘膜4b之后进行离子注入。在栅极GHV的侧壁中形成间隔物10a之后，在间隔物10a的表面和硅基板1的表面上形成氧化硅膜11和氮化硅膜12，并且将氧化硅膜 13形成并在其上平坦。由于氮化硅膜12在高击穿电压晶体管的源极/漏极区域1d的表面上没有直接接触，因此防止了热载体等的进入，从而提高了可靠性。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008085131A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2008085131A
公开(公告)日：2008-04-10
申请号：JP2006264376
申请日：2006-09-28
申请人： Toshiba Corp , 株式会社東芝
发明人： ENDO MASATO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , Y10S257/90
摘要： PROBLEM TO BE SOLVED: To prevent the higher resistance of a word line when a silicide is formed, the increasing nonuniformity of resistance due to heterogeneity in a metallic silicide film, and deterioration due to agglomeration, etc.
SOLUTION: A semiconductor memory comprises: a memory cell unit MCU having at least one memory cell MC with a structure where a floating gate 6 and control gates 10, 12, 16, 17 are laminated via an insulating film 5 on a semiconductor substrate, and also having at least one selection gate transistor S connected to the memory cell MC; a common source line SRC connected to one end of the memory cell unit MCU; and a bit line BL connected to the other end of the memory cell unit MCU. The control gates are formed to have a width being larger than that of the floating gate 6 in the longitudinal direction of the gates.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止形成硅化物时的字线的较高电阻，由于金属硅化物膜中的异质性导致的电阻不均匀性增加，以及由于聚集引起的劣化等。解决方案：半导体存储器包括：具有至少一个存储单元MC的存储单元单元MCU，其具有通过半导体衬底上的绝缘膜5层叠浮置栅极6和控制栅极10,12,16,17的结构，并且还具有连接到存储单元MC的至少一个选择栅极晶体管S; 连接到存储单元单元MCU的一端的公共源极线SRC; 以及连接到存储单元单元MCU的另一端的位线BL。控制栅极形成为具有比栅极的纵向方向上的浮动栅极6的宽度更大的宽度。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP4009331B2 Mos transistor and a method of manufacturing the same 失效
公开(公告)号：JP4009331B2
公开(公告)日：2007-11-14
申请号：JP11602495
申请日：1995-05-15
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：長來金
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7835 , H01L29/7836 , Y10S257/90 , Y10S438/948

8. 发明专利

JP2006294877A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006294877A
公开(公告)日：2006-10-26
申请号：JP2005113982
申请日：2005-04-11
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FUKAI TOSHINORI , SAKAKIYA AKIHITO
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/823864 , Y10S257/90
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device wherein a short channel effect in an n-type FET formation region is restrained and nFET characteristic is improved.
SOLUTION: The method comprises a process for forming a substrate protection film for covering an n-type FET formation region with a first gate electrode, and a p-type FET formation region with a second gate electrode; a process for forming a resist film to cover the n-type FET formation region and the p-type FET formation region and thereafter opening the p-type FET formation region by pattering the resist film; a process for exposing the semiconductor substrate surface by selectively removing the substrate protection film of the p-type FET formation region to leave it on the side wall of the second gate electrode; and a process for introducing impurities to the semiconductor substrate by using the resist film, the second gate electrode and the substrate protection film on the side wall of the second gate electrode as a mask and forming a pair of p-type extension regions in an area near the semiconductor substrate surface at both sides of the second gate electrode.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件的制造方法，其中抑制n型FET形成区域中的短沟道效应并提高nFET特性。解决方案：该方法包括用第一栅电极形成用于覆盖n型FET形成区的衬底保护膜和具有第二栅极的p型FET形成区的工艺; 形成用于覆盖n型FET形成区域和p型FET形成区域的抗蚀剂膜的工艺，然后通过图案化抗蚀剂膜来打开p型FET形成区域; 通过选择性地去除p型FET形成区域的衬底保护膜以将其留在第二栅电极的侧壁上来暴露半导体衬底表面的工艺; 以及通过使用第二栅电极的侧壁上的抗蚀剂膜，第二栅电极和衬底保护膜作为掩模将杂质引入到半导体衬底的工艺，并在区域中形成一对p型延伸区靠近第二栅电极两侧的半导体衬底表面。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006203232A Method for forming local connection/conductive line and structure thereof 审中-公开
标题翻译：形成本地连接/导电线及其结构的方法
公开(公告)号：JP2006203232A
公开(公告)日：2006-08-03
申请号：JP2006054044
申请日：2006-02-28
申请人： Micron Technology Inc , マイクロンテクノロジー, インク.
发明人： MANNING H MONTGOMERY
IPC分类号： H01L23/52 , H01L21/265 , H01L21/316 , H01L21/3205 , H01L21/76 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L27/088
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76829 , H01L21/76831 , H01L21/76895 , H01L23/485 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit including local connection, and to provide a method for manufacturing the semiconductor integrated circuit including the local connection. SOLUTION: A field insulating region 64 and an active area region 62 are formed on a semiconductor substrate 12. A trench is etched to a desired line shape in a field insulating material 66. A conductive material is deposited so that it fills the trench at least partially and a conductive line is formed inside. The field insulating material 66 is formed so that it has a LOCOS oxide film. COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2004152885A Semiconductor device and its fabricating method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004152885A
公开(公告)日：2004-05-27
申请号：JP2002314713
申请日：2002-10-29
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： KASUYA YOSHIKAZU
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923 , Y10S257/90
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a nonvolatile memory exhibiting a tolerance to deterioration when data is read/erased, and to provide its fabricating method.
SOLUTION: The semiconductor device 10 includes a memory domain 1000 constituting a memory array where nonvolatile memories are arranged in a matrix of a plurality of rows and columns. The nonvolatile memory includes a word gate 14 formed above the semiconductor layer 10 through a gate insulation layer 12, impurity layers 16 and 18 constituting a source region or a drain region formed on the semiconductor layer 10, and sidewall control gates 20 and 30 formed along one opposite side faces of the word gate 14, respectively. The control gates 20 and 30 have first control gates 20a and 30a and second control gates 20b and 30b touching each other wherein the first control gates 20a and 30a and the second control gates 20b and 30b are formed on insulation layers different in the thickness.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种包括在读/擦除数据时具有耐劣化性的非易失性存储器的半导体器件，并提供其制造方法。解决方案：半导体器件10包括构成存储器阵列的存储器域1000，其中非易失性存储器被排列成多个行和列的矩阵。非易失性存储器包括通过栅极绝缘层12形成在半导体层10上方的字栅14，构成半导体层10上形成的源极区或漏极区的杂质层16和18以及沿着半导体层10形成的侧壁控制栅极20和30 分别是字门14的一个相对的侧面。控制栅极20和30具有彼此接触的第一控制栅极20a和30a以及第二控制栅极20b和30b，其中第一控制栅极20a和30a以及第二控制栅极20b和30b形成在厚度不同的绝缘层上。版权所有（C）2004，JPO

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