专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS59115622A Frequency divider 失效
标题翻译：频率分配器
公开(公告)号：JPS59115622A
公开(公告)日：1984-07-04
申请号：JP22573582
申请日：1982-12-22
申请人： Sanyo Electric Co Ltd
发明人： KOJIMA KENICHI
IPC分类号： H03K23/58 , H03K5/00 , H03K23/00 , H03K23/66
CPC分类号： H03K23/66 , H03K5/00006
摘要： PURPOSE:To change optionally a frequency dividing ratio and to obtain a high-frequency dividing ratio without cascade connection of multi-stage by connecting a capacitor of different capacitance and a reference potential generating circuit respectively to a source and a drain of a transfer gate and connecting a level detecting circuit to one of them. CONSTITUTION:The reference voltage generating circuits 13, 14 charge respectively capacitors 11, 12 and the charge is moved between the capacitors 11, 12 by a count pulse at an input terminal (IN). Potentials VS(1) and VD(1) are expressed by an equation I when a gate 10 is turned on and a potential change DELTAVD(1) is expressed by an equation II, where VS, VD are potentials of the source and drain of the transfer gate 10, VS(0), VD(0) are their initial potentials respectively, VS(0) is a low potential and VD(0) is high potential. Further, when the gate 10 is turned off, the VS is changed again to the VS(0) and the gate 10 is turned on again, then a potential VD(2) is expressed by an equation III and the potential change DELTAVD(2) is expressed by an equation VI. Thus, the potential VD is decreased gradually in response to the number of times of turning- on of the gate 10, and when the gate 10 is turned on by (n) times and the VD is decreased less than a potential VX, then it is enough to detect by a level detecting circuit 15 that the potential VD is lower than the VX in order to form a frequency divider by 1/n.
摘要翻译：目的：通过将不同电容的电容器和参考电位产生电路分别连接到传输门的源极和漏极，可以选择性地改变分频比并获得高分频比，而不需要级联多级，将电平检测电路连接到其中一个。构成：参考电压产生电路13,14分别对电容器11,12充电，并且电荷在电容器11,12之间通过输入端（IN）处的计数脉冲移动。当门10导通时，电位VS（1）和VD（1）由等式I表示，并且电位变化DELTAVD（1）由等式II表示，其中VS，VD是源极和漏极的电位传输门10，VS（0），VD（0）分别为其初始电位，VS（0）为低电位，VD（0）为高电位。此外，当门10关断时，VS再次改变为VS（0），并且门10再次导通，则电位VD（2）由等式III表示，电位变化DELTAVD（2 ）由方程式VI表示。因此，响应于栅极10的导通次数，电位VD逐渐减小，并且当栅极10接通（n）次并且VD减小到小于电位VX时，则其为了通过1 / n形成分频器，电平检测电路15足以检测电位VD低于VX。

2. 发明专利

JPS5921131A Variable frequency divider 失效
标题翻译：可变频分频器
公开(公告)号：JPS5921131A
公开(公告)日：1984-02-03
申请号：JP13022982
申请日：1982-07-28
申请人： Toshiba Corp
发明人： KUDOU KIYOUICHI
IPC分类号： H03K23/64 , H03K23/66 , H03K21/36
CPC分类号： H03K23/66
摘要： PURPOSE:To realize quantitative control and to ensure an assured operation with no effect given by component elements, by taking an input control signal temporarily into a buffer circuit and then delivering a selecting signal with a limited timing phase. CONSTITUTION:The L level is transferred synchronously with an output signal 16 for both positive and negative selecting signals 28 and 29 which are equal to the output of a buffer circuit 21 when no positive nor negative signal exists. As a result, an output signal 23 of a selecting circuit 19 selects a reference phase signal 30 and latches 20 it to supply it as a clear signal of a shift register circuit 18. Thus a signal 16 of 3T0 is generated to a basic frequency signal period T0. When a positive signal 14 is generated, the H level is transferred for the signal 28. Then the signal 23 selects a positive compensated phase signal 31 and then supplies a clear signal to the circuit 21 via the circuit 18 and a clear circuit 26. As a result, the signal 16 has a period 4T0. Then a negative signal 15 is generated, and the L level is transferred for the signal 29. The signal 23 produces a negative compensated phase signal 32. As a result, the signal 16 has a period 2T0.
摘要翻译：目的：通过将输入控制信号暂时取入缓冲电路，然后以有限的定时相位传送选择信号，实现定量控制，确保不受组件元件影响的有保证的操作。构成：当没有正信号和负信号时，L电平与正和负选择信号28和29的输出信号16同步传送，等于缓冲电路21的输出。结果，选择电路19的输出信号23选择参考相位信号30并锁存它20以将其作为移位寄存器电路18的清除信号提供。因此，将3T0的信号16产生到基本频率信号时期T0。当产生正信号14时，为信号28传送H电平。然后，信号23选择正补偿相位信号31，然后通过电路18和清除电路26向电路21提供清除信号。结果，信号16具有周期4T0。然后产生负信号15，并且信号29传送L电平。信号23产生负补偿相位信号32.结果，信号16具有周期2T0。

3. 发明专利

JPS5737932A Variable frequency divider 失效
标题翻译：可变频分频器
公开(公告)号：JPS5737932A
公开(公告)日：1982-03-02
申请号：JP11207180
申请日：1980-08-14
申请人： Toshiba Corp
发明人： WATANABE FUKUYOSHI
IPC分类号： H03K23/66 , H03K21/36
CPC分类号： H03K23/66
摘要： PURPOSE:To increase the response speed of switching at frequency dividing ratio switching, by forming pulses having T times the frequency of input pulse frequency, frequency-dividing this as the input clock pulse, and frequency-dividing the output to 1/T. CONSTITUTION:Frequency of an input pulse CP is multiplied by T at a double frequency circuit 11 to form an input clock pulse CK and this is inputted to a binary counter 12. A frequency dividing data set to a latch circuit 13 is decoded at a decoder 14 and the decoded frequency dividing value is inputted to a coincidence detection circuit 15. The circuit 15 compares the frequency dividing value with the count value from the counter 12, the coincidence of both the data is detected to output the coincidence detection pulse to a 1/T frequency-dividing circuit 16, and the counter 12 is reset with the coincidence detection pulse and a frequency dividing ratio data is fetched to the circuit 13. Since the input pulse is frequency-divided into 1/T at the circuit 16 and makes output, when the frequency dividing ratio is switched, the switching response time can be reduced to 1/T.
摘要翻译：目的：为了提高分频比切换的响应速度，通过形成具有T倍输入脉冲频率频率的脉冲，将其分频为输入时钟脉冲，并将输出分频为1 / T。构成：输入脉冲CP的频率在双倍频率电路11处与T相乘以形成输入时钟脉冲CK，并将其输入到二进制计数器12.设置到锁存电路13的分频数据在解码器 14，并且解码分频值被输入到重合检测电路15.电路15将分频值与来自计数器12的计数值进行比较，检测到两个数据的一致，以将符合检测脉冲输出为1 / T分频电路16，并且计数器12用一致检测脉冲复位，并且将分频比数据取出到电路13.由于输入脉冲在电路16处被分频为1 / T，并且输出，当切换分频比时，切换响应时间可以减少到1 / T。

4. 发明专利

JPS54147765A Frequency division circuit 失效
标题翻译：频率分段电路
公开(公告)号：JPS54147765A
公开(公告)日：1979-11-19
申请号：JP5595278
申请日：1978-05-11
申请人： Toshiba Corp
发明人： SUZUKI YASOJI , TAKADA MINORU , IWAMOTO YOSHIHIRO
IPC分类号： H03K23/00 , H03K23/40 , H03K23/64 , H03K23/66
CPC分类号： H03K23/66
摘要： PURPOSE:To enable stable high speed operation independently of operation speed of the OR circuit, by selectively supplying the count output of the counter circuit integrated to the OR circuit. CONSTITUTION:The clock pulse CK is inputted, and either one of the count output signals consisting of 10-bit of Q0 to Q9 is parallelly fed to the NOR gate 21 incorporated in the different integrated circuit from the counter circuit 20 integrated, e.g., Q3 and Q8. Accordingly, the output signal of the NOR gate is not set during only the presence of the signals Q3 and Q8, that is, once every five CK's, and no CK is frequency-divided. In this case, the frequency of the signals Q3 and Q8 is sufficiently lower than the frequency of CK. Even if the wiring capacitance between the circuit 20 and the NOR gate 21 is greater, the NOR gate is stably operated. Further, by changing the frequency dividing ratio of CK, the count output signal of the circuit 20 inputted to the NOR gate 21 can arbitrarily be selected.
摘要翻译：目的：通过选择性地提供与OR电路集成的计数器电路的计数输出，实现与OR电路运行速度无关的稳定高速运行。构成：时钟脉冲CK被输入，由10位的Q0至Q9组成的计数输出信号中的任一个被并入到集成在不同的集成电路中的NOR门21，例如Q3 和Q8。因此，仅在存在信号Q3和Q8期间，即不存在每个CK，并且没有CK被分频，NOR门的输出信号不被设置。在这种情况下，信号Q3和Q8的频率足够低于CK的频率。即使电路20和NOR门21之间的配线电容较大，也可以稳定地进行NOR门的操作。此外，通过改变CK的分频比，可以任意地选择输入到或非门21的电路20的计数输出信号。

5. 发明专利

JP2013027050A Dynamic frequency control using coarse clock gating 有权
标题翻译：动态时钟频率控制
公开(公告)号：JP2013027050A
公开(公告)日：2013-02-04
申请号：JP2012173368
申请日：2012-07-18
申请人： Apple Inc , アップルインコーポレイテッド
发明人： JAMES WANG , LAW PATRICK Y
IPC分类号： H04L7/00 , G06F1/04 , G06F1/08
CPC分类号： G06F1/08 , G06F1/324 , H03K23/66 , Y02D10/126
摘要： PROBLEM TO BE SOLVED: To provide a method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit.SOLUTION: In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.
摘要翻译：要解决的问题：提供一种使用时钟门控电路来控制时钟信号的频率的方法和装置。解决方案：在一个实施例中，根时钟信号和使能信号被提供给时钟门控电路。时钟门控电路被配置为当使能信号被断言时提供操作时钟信号（基于根时钟信号）。当使能信号被取消置位时，操作时钟信号被禁止。可以通过在每N个时钟周期之一断言使能信号，以降低的频率输出操作时钟信号的频率。此外，可以通过改变使能信号相对于根时钟信号的确认速率来动态地改变操作时钟信号的频率，而不会暂停接收操作时钟信号的功能单元的操作。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2008510428A Multi-stage programmable Johnson counter 审中-公开
公开(公告)号：JP2008510428A
公开(公告)日：2008-04-03
申请号：JP2007527840
申请日：2005-07-29
申请人：インテルコーポレイション
发明人：ウォン，ケン , ワン，フェン
IPC分类号： H03K23/64 , H03K5/14 , H03K23/54 , H03K23/66 , H03L7/183
CPC分类号： H03L7/183 , H03K23/542 , H03K23/66
摘要：カウンタは複数のマルチプレクサを用いて選択可能な分周係数を有する。このカウンタはインバータと、選択可能な段遅延を有する縦続遅延段とを含んでいる。インバータは最後の１つの遅延段の段出力を最初の１つの遅延段の段入力に接続している。各遅延段は商信号を受け取る段入力、各々が段入力から商信号を受け取るように結合された、相異なる付随のパス遅延を有する少なくとも２つのパス、及びマルチプレクサを含んでいる。段遅延の１つを選択するために、マルチプレクサは少なくとも２つのパスの１つからの商信号を選択的に段出力に伝達するように結合されている。

7. 发明专利

JPS59215127A Signal synthesizing circuit 失效
标题翻译：信号合成电路
公开(公告)号：JPS59215127A
公开(公告)日：1984-12-05
申请号：JP8873883
申请日：1983-05-20
申请人： Seiko Instr & Electronics Ltd
发明人： YAGI SHIGEKI
IPC分类号： G04G3/02 , G04F5/00 , H03K21/40 , H03K23/66 , H03K21/36
CPC分类号： H03K23/66
摘要： PURPOSE:To lower operating input frequency, to simplify a circuit constitution and to reduce power consumption by adjusting an output pulse width transmitted from a counter every time a delay compensating counter counts up. CONSTITUTION:A signal generator 10 transmits a reference signal S11, a signal S2 that is inverted signal S1, a signal S3 that is advanced in phase signal S1 by 1/4 period, and a signal S4 that is inverted signal S3, to a signal input circuit 11. The signals S1-S4 are selected cyclicly from the circuit 11, and fed to the post-stage by the control of an input signal selecting circuit 13. A counter 12 counts decimally an output of the circuit 11 and also outputs a reference signal. Further, a count-up signal of the counter 12 is fed to a delay compensating counter 14, which corrects the delay in the output pulse outputted from the counter every time the counter 14 counts the 25 signals. Then, the frequency of the input pulse signal is decreased.
摘要翻译：目的：降低工作输入频率，简化电路结构，并通过调整每次延迟补偿计数器递增计数器发送的输出脉冲宽度来降低功耗。构成：信号发生器10将参考信号S11，反相信号S1的信号S2，将相位信号S1前进1/4信号的信号S3和反相信号S3的信号S4发送到信号输入电路11.信号S1-S4从电路11循环选择，并通过输入信号选择电路13的控制馈送到后级。计数器12十进制计数电路11的输出，并输出一个参考信号。此外，计数器12的向上计数信号被馈送到延迟补偿计数器14，延迟补偿计数器14每当计数器14计数25个信号时校正从计数器输出的输出脉冲的延迟。然后，输入脉冲信号的频率降低。

8. 发明专利

JPS5912634A Counting circuit 失效
标题翻译：计数电路
公开(公告)号：JPS5912634A
公开(公告)日：1984-01-23
申请号：JP12160282
申请日：1982-07-13
申请人： Nec Corp
发明人： NEGISHI TAKESHI
IPC分类号： H03K23/64 , H03K23/66 , H03K21/36
CPC分类号： H03K23/66
摘要： PURPOSE:To change the period of a counting section with simple constitution, by outputting a coincidence pulse from a collating section when a count value output of the counting section is coincident with a control signal and returning the pulse to a reset terminal of the counting section for resetting the counting section. CONSTITUTION:The control signal given in the same form as that of the count value output of a counting circuit 1 is inputted to a collating circuit 2 from a terminal 13, and the collating circuit 12 outputs a coincidence output pulse when this control signal is coincident with the counting value output from the circuit 1. The circuit 1 is reset to a predetermined initial value by returning this coincidence output pulse to the circuit 1. The circuit 1 performs counting by regarding values ranging from the initial value to the value of the control signal inputted to the circuit 2 to output the coincidence output pulse as a period in this way. Thus, various periods are formed easily and changed by giving a suitable value as the control signal.
摘要翻译：目的：为了以简单的结构改变计数部分的周期，当计数部分的计数值输出与控制信号一致时，通过从对照部分输出一致脉冲，并将脉冲返回到计数部分的复位端用于重置计数部分。构成：以与计数电路1的计数值输出相同的形式给出的控制信号从端子13输入到对照电路2，并且当该控制信号一致时，对照电路12输出一致的输出脉冲从电路1输出的计数值。通过将该符合输出脉冲返回到电路1，将电路1复位到预定的初始值。电路1通过将从初始值到控制值的范围的值进行计数输入到电路2的信号作为周期输出一致的输出脉冲。因此，通过给出合适的值作为控制信号，容易地形成各种周期并进行变化。

9. 发明专利

JPS58219831A Circuit for detecting coincidence of output from counter 失效
标题翻译：用于检测计数器输出信号的电路
公开(公告)号：JPS58219831A
公开(公告)日：1983-12-21
申请号：JP10271082
申请日：1982-06-15
申请人： Matsushita Electric Works Ltd
发明人： KOMODA TAKUYA
IPC分类号： H03K23/66
CPC分类号： H03K23/66
摘要： PURPOSE:To compensate time shear until the stabilization of each bit in a counter circuit at the time of digit shifting by inputting the output of each bit of the counter consisting of plural bits to a gate for detecting coincidence through a sequential delaying element. CONSTITUTION:The initial value of a counter circuit consisting of 9 bits is set up by initial value input terminals PRE1-9, and when all outputs A'-I' are ''1'', i.e. coincidence of the minimum value is detected, the outputs of respective inverters G5-G7 are delayed by stages until the state of respective bits is stabilized by using the characteristic that the delay time of a delay circuit of one gate in an NAND gate is 25ns, which is sufficiently smaller than a clock period (10mus). Since the delay of an output from the inverter G7 is 25ns by the superposition of outputs H', G', F', the outputs of the inverters G5, G6 are delayed by 25ns or more and the outputs of the inverters G5, G7 are delayed by 50ns or more in stages. Consequently, incorrect detection of coincidence is prevented at the time of shifting from the upper digit to the lower digit.
摘要翻译：目的：通过将由多个位组成的计数器的每个位的输出输入到用于通过顺序延迟元件的一致检测的门，来补偿时间剪切直到数字移位时的计数器电路中每个位的稳定。构成：由9位组成的计数器电路的初始值由初始值输入端PRE1-9设置，当所有输出A'-I'为“1”时，即检测到最小值的一致，各个反相器G5-G7的输出被逐级延迟，直到各个位的状态稳定为止，使用NAND门中的一个门的延迟电路的延迟时间为25ns，这比时钟周期（10mus）。由于通过输出H'，G'，F'的叠加，来自反相器G7的输出的延迟为25ns，所以反相器G5，G6的输出被延迟25ns以上，反相器G5，G7的输出为延迟了50ns以上的阶段。因此，在从高位数字转换到下位数时，防止了错误的重合检测。

10. 发明专利

JP6242228B2 クロック生成方法およびクロック生成回路有权
公开(公告)号：JP6242228B2
公开(公告)日：2017-12-06
申请号：JP2014020557
申请日：2014-02-05
申请人：株式会社メガチップス
发明人：鰐渕智弘
IPC分类号： G06F1/10 , H03K5/15 , G06F1/08
CPC分类号： H03L7/18 , G06F1/08 , G06F1/10 , H03K5/153 , G06F1/12 , H03K23/66

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式