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1. 发明专利

JP2013106062A Frequency divider circuit and pll circuit 有权
标题翻译：频率分路电路和PLL电路
公开(公告)号：JP2013106062A
公开(公告)日：2013-05-30
申请号：JP2011246362
申请日：2011-11-10
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： OKADA KENICHI , AHMED MAGDY HASSAN MUSA
IPC分类号： H03K27/00 , H03K5/00 , H03K23/52 , H03K23/54 , H03L7/08
CPC分类号： H03L5/00 , H03B19/06 , H03K3/0322 , H03L7/183 , H03L7/24
摘要： PROBLEM TO BE SOLVED: To achieve an injection-locked frequency divider circuit which has such a circuit size as to be subject a signal to 1/2 frequency division, 1/8 frequency division and further 1/8 frequency division with low power consumption.SOLUTION: A frequency divider circuit has: a ring oscillator 11 having an even number N of delay elements DL1 to DL4; and a synchronization signal injection circuit for generating a synchronization signal from an input oscillation signal, and injecting the generated synchronization signal into at least a part of the plurality of delay elements. The frequency divider circuit outputs a frequency-divided signal of the input oscillation signal. One terminal to be controlled of a frequency divider transistor for turning the delay elements on/off is an injection node, and the synchronization signal injection circuit has injection differential pairs M1 to M4 having two auxiliary injection transistors provided in parallel to one another so as to be connected to the injection node of the two delay elements separated by M/2 pieces, and signal injection transistors M5 and M6 which allow the input oscillation signals RF4+ and RF4- to be input to a control terminal, and are connected to the injection differential pairs so as to generate a differential signal of the input oscillation signal in the connection node between the signal injection transistors and the injection node of the injection differential pairs.
摘要翻译：要解决的问题：为了实现具有这样的电路尺寸的注入锁定分频器电路，该电路的大小被分频为1/2分频，1/8分频，进一步为1/8分频，低能量消耗。解决方案：分频器电路具有：具有偶数N个延迟元件DL1至DL4的环形振荡器11; 以及同步信号注入电路，用于根据输入的振荡信号产生同步信号，并将产生的同步信号注入至多个延迟元件的一部分。分频器电路输出输入振荡信号的分频信号。用于使延迟元件导通/截止的分频晶体管的一个端子是注入节点，同步信号注入电路具有注入差分对M1至M4，其具有彼此平行设置的两个辅助注入晶体管，以便连接到由M / 2个分离的两个延迟元件的注入节点，并且允许输入振荡信号RF4 +和RF4-的信号注入晶体管M5和M6被输入到控制端，并且连接到注入差分以在信号注入晶体管和注入差分对的注入节点之间的连接节点中产生输入振荡信号的差分信号。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP5372114B2 Divider and pll circuit 有权
公开(公告)号：JP5372114B2
公开(公告)日：2013-12-18
申请号：JP2011246362
申请日：2011-11-10
申请人：株式会社半導体理工学研究センター
发明人：健一岡田 , マグディハッサンムサアハメド
IPC分类号： H03K27/00 , H03K5/00 , H03K23/52 , H03K23/54 , H03L7/08
CPC分类号： H03L5/00 , H03B19/06 , H03K3/0322 , H03L7/183 , H03L7/24
摘要： A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.

3. 发明专利

JP2008275407A Semiconductor integrated circuit and method of inspecting semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路及其半导体集成电路检测方法
公开(公告)号：JP2008275407A
公开(公告)日：2008-11-13
申请号：JP2007118261
申请日：2007-04-27
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OGAWA HAYATO
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： H03B19/06 , G01R31/31727 , H03L7/07 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To reduce an inspection time of PLLs in a semiconductor integrated circuit loaded with a plurality of PLLs.
SOLUTION: The circuit includes PLLs to the number of S (S is an integer satisfying the inequality: S≥2), and is constituted so that the (k-1)-th PLL 12
(k-1) (k is an integer satisfying the inequalities: 2≤k≤S) is connected in series to the k-th PLL 12
k . Hereby, PLLs to the number of S can be inspected at the first try, and the inspection time of PLLs in LSI loaded with the plurality of PLLs can be reduced.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：减少加载有多个PLL的半导体集成电路中的PLL的检查时间。解决方案：该电路包括S个数的PLL（S是满足不等式S≥2的整数），并且构成为使得第（k-1）个PLL 12（k-1））（k是满足不等式的整数：2≤k≤S）与第k个PLL 12 串联连接。因此，可以在第一次尝试时检查到S个数的PLL，并且可以减少装载有多个PLL的LSI中的PLL的检查时间。版权所有（C）2009，JPO＆INPIT

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