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1. 发明专利

JP2007288392A Limiter circuit 有权
标题翻译：限制电路
公开(公告)号：JP2007288392A
公开(公告)日：2007-11-01
申请号：JP2006111627
申请日：2006-04-14
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OGAWA HAYATO
IPC分类号： H03G11/00
CPC分类号： H03G11/00
摘要： PROBLEM TO BE SOLVED: To provide a limiter circuit which is capable of limiting a voltage of an analog signal and has errors of an output voltage suppressed. SOLUTION: In a limiter circuit 10, an input voltage V IN is taken as a reverse phase input of a differential amplifier circuit 5, and an output of the differential amplifier circuit 5 is connected to a gate of a transistor MP1, and a drain of the transistor MP 1 is connected to a drain of another transistor M1, and a source of the transistor M1 is connected to one end of a constant current source 4 and is taken as an in-phase input of the differential amplifier circuit 5, and the differential amplifier circuit 5 and transistors MP1 and M1 constitute a feedback line, and a voltage of the source of the transistor M1 is taken as an output voltage V OUT of the limiter circuit 10. A fixed voltage VL is applied to a gate of the transistor M1 included in the feedback line, by a voltage source 6. When the input voltage V IN exceeds a voltage VL-VT1 wherein VT1 is a threshold voltage of the transistor M1, the transistor M1 is turned off to cut off the feedback line, and the output voltage V OUT is limited to VL-VT1. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种限制电路，其能够限制模拟信号的电压并且抑制输出电压的误差。
解决方案：在限幅电路10中，将输入电压V IN 作为差分放大电路5的反相输入，差分放大电路5的输出连接到晶体管MP1的栅极，晶体管MP1的漏极连接到另一个晶体管M1的漏极，晶体管M1的源极连接到恒流源4的一端并被同时成为差分放大电路5的输入，差分放大电路5和晶体管MP1，M1构成反馈线，晶体管M1的电压作为输出电压V OUT 限制电路10.固定电压VL通过电压源6施加到包括在反馈线中的晶体管M1的栅极。当输入电压V IN 超过电压VL-VT1时，其中 VT1是晶体管M1的阈值电压，晶体管M1截止以截止反馈线输出电压V OUT 被限制为VL-VT1。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008275407A Semiconductor integrated circuit and method of inspecting semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路及其半导体集成电路检测方法
公开(公告)号：JP2008275407A
公开(公告)日：2008-11-13
申请号：JP2007118261
申请日：2007-04-27
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OGAWA HAYATO
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： H03B19/06 , G01R31/31727 , H03L7/07 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To reduce an inspection time of PLLs in a semiconductor integrated circuit loaded with a plurality of PLLs.
SOLUTION: The circuit includes PLLs to the number of S (S is an integer satisfying the inequality: S≥2), and is constituted so that the (k-1)-th PLL 12
(k-1) (k is an integer satisfying the inequalities: 2≤k≤S) is connected in series to the k-th PLL 12
k . Hereby, PLLs to the number of S can be inspected at the first try, and the inspection time of PLLs in LSI loaded with the plurality of PLLs can be reduced.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：减少加载有多个PLL的半导体集成电路中的PLL的检查时间。解决方案：该电路包括S个数的PLL（S是满足不等式S≥2的整数），并且构成为使得第（k-1）个PLL 12（k-1））（k是满足不等式的整数：2≤k≤S）与第k个PLL 12 串联连接。因此，可以在第一次尝试时检查到S个数的PLL，并且可以减少装载有多个PLL的LSI中的PLL的检查时间。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2005277472A Pll test equipment 审中-公开
标题翻译： PLL测试设备
公开(公告)号：JP2005277472A
公开(公告)日：2005-10-06
申请号：JP2004083627
申请日：2004-03-22
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OGAWA HAYATO
IPC分类号： G01R31/28 , H03L7/08
摘要： PROBLEM TO BE SOLVED: To provide test equipment performing DC detection of failure in one or both circuits by comparing the output waveform from two arbitrary phase synchronization circuits in a semiconductor circuit mounting a plurality of phase synchronization circuits represented by PLL. SOLUTION: In a semiconductor circuit mounting a plurality of phase synchronization circuits, a delay circuit and a comparison circuit are formed on the same chip. In two phase synchronization circuits being inspected, phase of a signal entering any one circuit is delayed through a delay circuit. The comparison circuit detects phase shift by comparing the output signals from first and second phase synchronization circuits and informs failure of circuit by outputting a DC signal. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过比较安装由PLL表示的多个相位同步电路的半导体电路中的两个任意相位同步电路的输出波形来提供在一个或两个电路中执行故障的直流检测的测试设备。解决方案：在安装多个相位同步电路的半导体电路中，在同一芯片上形成延迟电路和比较电路。在正在检查的两个相位同步电路中，进入任何一个电路的信号的相位通过延迟电路被延迟。比较电路通过比较来自第一和第二相位同步电路的输出信号来检测相移，并通过输出DC信号通知电路故障。版权所有（C）2006，JPO＆NCIPI

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