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1. 发明专利

JPS5911684A Forming method for buried gate of semiconductor device 失效
标题翻译：半导体器件的栅极形成方法
公开(公告)号：JPS5911684A
公开(公告)日：1984-01-21
申请号：JP12046082
申请日：1982-07-13
申请人： Toyo Electric Mfg Co Ltd
发明人： MURAOKA KIMIHIRO
IPC分类号： H01L21/335 , H01L29/80
CPC分类号： H01L29/66416 , H01L29/80
摘要： PURPOSE:To obtain the gate forming method, which jointly uses a diffusion method and an epitaxial growth method and particularly perform the epitaxial growth effectively and skillfully, by forming the gate by filling grooves with a silicon single crystal of a conduction type reverse to a silicon substrate so that the longitudinal sections of the grooves have three concentration distributions increasing toward the bottom sides from the upper surface sides and laminating a silicon single crystal of the same conduction type as the silicon substrate on the gate. CONSTITUTION:P type diffusion layers 7 are formed on the insides of recessed surfaces of the grooves 6' formed to the substrate 1'', the groove 6' sections are buried with P type epitaxial layers, and impurity concentration at three steps increasing toward lower surfaces from upper surfaces is given. That is, surface concentration is (1X10 )(atoms/cc) in the P type diffusion layers 7 formed through the diffusion method, and boron is doped to silicon tetrachloride from recessed bottoms having the surface concentration and the P type epitaxial growth layers of boron concentration of a (1X10 )(atoms/cc) order are grown in 10(mum). A P type epitaxial growth layer of boron concentration of a (1X10 ) (atoms/cc) order is grown continuously on the P type epitaxial growth layers in 5-7(mum). Accordingly, the groove 6 sections of 15(mum) depth are buried, and gate 4'' regions can be formed by using the diffusion method and the epitaxial growth method.
摘要翻译：目的：为了获得共同使用扩散方法和外延生长方法的栅极形成方法，特别是有效和巧妙地进行外延生长，通过用与硅相反的导电类型的硅单晶填充沟槽来形成栅极基板，使得槽的纵向部分具有从上表面侧朝向底侧增加的三个浓度分布，并且将与硅基板相同导电类型的硅单晶层叠在栅极上。构成：在形成于基板1“的槽6'的凹陷表面的内侧形成有P型扩散层7，凹槽6'被P型外延层掩埋，并且三级的杂质浓度朝向下方增加给出了上表面的表面。也就是说，通过扩散法形成的P型扩散层7中的表面浓度为（1×10 19）（原子/ cc），并且从具有表面浓度和P型外延生长的凹陷底部将硼掺杂到四氯化硅中（1×10 19）（原子/ cc）级的硼浓度层在10（mum）中生长。在5-7（mum）的P型外延生长层上连续生长（1×10 17）（原子/ cc）的硼浓度的P型外延生长层。因此，埋入15（mum）深度的槽6部分，并且可以通过使用扩散法和外延生长法形成栅极4“区域。

2. 发明专利

JPS59108346A Manufacture of solid-state image pickup device 失效
标题翻译：固态图像拾取器件的制造
公开(公告)号：JPS59108346A
公开(公告)日：1984-06-22
申请号：JP21892382
申请日：1982-12-14
申请人： Fuji Photo Film Co Ltd , Junichi Nishizawa
发明人： NISHIZAWA JIYUNICHI , SUZUKI SOUBEE , IKEDA MITSURU , MUTOU HIDEKI
IPC分类号： H01L21/265 , H01L21/335 , H01L27/146 , H01L29/167 , H01L29/772 , H01L29/80 , H01L31/112 , H04N5/335
CPC分类号： H01L29/66416 , H01L21/26506 , H01L29/167 , H01L29/7722 , H01L31/1126
摘要： PURPOSE:To diffuse an impurity thermally while giving anisotropy in the depth direction by implanting the ions of an element lighter than an impurity element doped in a plurality of different implantation depth and annealing the element. CONSTITUTION:The impurity as an acceptor such as a III group element, such as B, Al, Ga or the like is doped to an n layer 12 through thin SiO2 layer sections 26 in sections corresponding to gate regions 16 and 18 or 20. The ions of the element lighter than the impurity, which is implanted to the sections corresponding to the gate regions 16 and 18 or 20, such as B are implanted. A structure 92 annealed at a low temperature is transferred to a forming process for a source region 14. A phosphorus silicate glass layer 38 is formed to the surface of the structure 92, the section corresponding to the control gate region 16 is removed selectively through wet etching together with an SiO2 layer 24 under the section, and an inter-layer insulating layer 38 is formed. Others are removed selectively through etching with the exception of the sections corresponding to the shielding gate regions 18, and a light shielding layer 56 and a shielding gate electrode 54 are formed.
摘要翻译：目的：通过注入比在多个不同注入深度掺杂的杂质元素更轻的元素的离子并对该元件进行退火，使热量散布杂质，同时在深度方向上产生各向异性。构成：在对应于栅极区域16和18的部分中，通过薄SiO 2层部分26将诸如B，Al，Ga等的III族元素的受体杂质掺杂到n +层12或植入到对应于栅极区域16和18或20（例如B）的部分中的比杂质更轻的元素的离子被植入。将在低温下退火的结构92转移到源极区域14的形成过程。在结构92的表面上形成磷硅酸盐玻璃层38，对应于控制栅极区域16的部分通过湿气选择性地去除在该截面下与SiO 2层24一起蚀刻，形成层间绝缘层38。除了与屏蔽栅极区域18相对应的部分以外，通过蚀刻选择性地除去其他部分，并且形成遮光层56和屏蔽栅极电极54。

3. 发明专利

JP4777630B2 Semiconductor device 有权
公开(公告)号：JP4777630B2
公开(公告)日：2011-09-21
申请号：JP2004272955
申请日：2004-09-21
申请人：株式会社デンソー , 株式会社日立製作所
发明人：ラジェシュクマール丸汎 , 孝純大柳 , 剛山本 , 敏之森下 , 篤雄渡辺
IPC分类号： H01L29/80 , H01L21/28 , H01L21/337 , H01L29/808
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083

4. 发明专利

JPS61104672A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61104672A
公开(公告)日：1986-05-22
申请号：JP22588584
申请日：1984-10-29
申请人： Res Dev Corp Of Japan
发明人： ISHIYUTOBUAN BAARUSHIYONI
IPC分类号： H01L29/80 , H01L21/335 , H01L29/10 , H01L29/772
CPC分类号： H01L29/66416 , H01L29/1066 , H01L29/7722
摘要： PURPOSE: To enable the ready formation of cut-in gate structure by a method wherein cut-in parts are formed by utilizing side etching through isotropic etching, and then gates are formed by adding impurities through the apertures with the same mask.
CONSTITUTION: An epitaxial layer 51 is formed on an Si substrate 50, which substrate is subjected to slice etching by being masked with an SiO
2 film 52. Next, the film 52 is removed, and an SiO
2 film 52 is produced on the surface by thermal oxidation; then, only the part of SIT formation is removed by etch ing. A poly Si film 54 is formed by CVD, and a doping region 54A is provided by As
+ ion implantation with the mask of a resist layer 55. The resist layer 55 is removed, and a thin SiO
2 film 56 is formed by thermal oxidation; there after, an Si
3 N
4 film 57 is formed by CVD. Apertures to form the gate region are provided by etching, and this part is processed into a desired cut-in gate shape by isotropic etching, thus forming the overhang 57A structure. After a thin thermal oxide film 53' to prevent the channeling of the next ion implanta tion is formed at the cut-in part, B
+ ions are implanted into the formation of gates 59.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了能够通过利用通过各向同性蚀刻的侧面蚀刻形成切入部分的方法来形成切入栅极结构，然后通过使用相同掩模的孔加入杂质形成栅极。构成：外延层51形成在Si衬底50上，该衬底通过用SiO 2膜52掩模进行切片蚀刻。接下来，去除膜52，并且通过热量在表面上产生SiO 2膜52 氧化; 那么只有SIT形成的一部分通过蚀刻去除。通过CVD形成多晶硅膜54，并且通过As +离子注入提供掺杂区域54A和抗蚀剂层55的掩模。去除抗蚀剂层55，并且通过热量形成薄的SiO 2膜56 氧化; 之后，通过CVD形成Si 3 N 4膜57。通过蚀刻提供形成栅极区的孔，并且通过各向同性蚀刻将该部分加工成所需的切入栅极形状，从而形成突出部57A结构。在薄的热氧化膜53'之后，在切入部分形成下一个离子注入的沟道，B +离子被注入到栅极59的形成中。

5. 发明专利

JPS59108363A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59108363A
公开(公告)日：1984-06-22
申请号：JP21775482
申请日：1982-12-14
申请人： Junichi Nishizawa , Olympus Optical Co Ltd
发明人： MORIMOTO MASAMICHI , NISHIZAWA JIYUNICHI , SUZUKI SOUBEE , TAMAMUSHI NAOSHIGE
IPC分类号： H01L21/225 , H01L21/32 , H01L21/335 , H01L27/146 , H01L29/772 , H01L29/80
CPC分类号： H01L29/66416 , H01L21/2257 , H01L21/32 , H01L29/7722 , H01L29/80
摘要： PURPOSE: To obtain a semiconductor device having electrode regions separated mutually in the lateral direction on the upper side of a semiconductor main body by a method wherein a polycrystalline silicon layer is oxidized removing the upper parts of the electrode regions to be formed in the semicondutor main body.
CONSTITUTION: A polycrystalline silicon layer 24 is adhered on a semiconductor main body 21 consisting of an n
- type layer 23 formed by epitaxial deposition on an n
- type silicon substrate 22, and a silicon nitride layer 25 is adhered on the polycrystalline silicon layer 24 thereof. The silicon nitrode layer parts on the upper side of electrode regions only are left, the other silicon nitrode layer parts are removed, and the exposed polycrystalline silicon layer parts are oxidized to obtain silicon oxide layer 26. The silicon nitride layer parts and the polycrystalline silicon layer parts existing thereunder are removed. The upper parts of ion diffusing regions 28 are oxidized to close the windows of the parts thereof, ion driving-in of the ion diffusion regions 28 is performed according to oxidation thereof to form gate regions 29, and remaining silicon nitride layer is removed. Ions of phosphorus or arsenic are implanted in the polycrystalline silicon layer 24 to form a doped polycrystalline silicon layer, and at the same time, ions are implanted also in the epitaxial layer 23 through the polycrystalline silicon layer thereof to form a source region 30.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了获得半导体主体的上侧的横向相互分离的电极区域的半导体器件，其中氧化多晶硅层，去除要形成在半导体主体中的电极区域的上部身体。构成：将多晶硅层24粘附在由在n型硅基板22上通过外延沉积形成的n型层23构成的半导体主体21上，并且氮化硅层25粘附在多晶硅层24。仅留下电极区域上侧的硅硝基层部分，除去另一个硅硝基层部分，暴露的多晶硅层部分被氧化，得到氧化硅层26.氮化硅层部分和多晶硅存在的层部件被删除。离子扩散区域28的上部被氧化以封闭其部分的窗口，离子扩散区域28的离子驱入根据其氧化进行以形成栅极区域29，并且去除剩余的氮化硅层。将磷或砷的离子注入多晶硅层24中以形成掺杂的多晶硅层，同时通过其多晶硅层将离子注入到外延层23中以形成源极区30。

6. 发明专利

JPS5936971A Buried gate formation of semiconductor device 失效
标题翻译：二极管形成半导体器件
公开(公告)号：JPS5936971A
公开(公告)日：1984-02-29
申请号：JP14695782
申请日：1982-08-26
申请人： Toyo Electric Mfg Co Ltd
发明人： MURAOKA KIMIHIRO
IPC分类号： H01L21/335 , H01L21/74 , H01L29/80
CPC分类号： H01L29/66416 , H01L29/80
摘要： PURPOSE:To prevent the closure of channels by enhancing the concentration at the center of the gate by a method wherein heat treatment is performed after epitaxial growth. CONSTITUTION:Cut grooves 6 are formed by utilizing an oxide film 2 on an N type substrate. Next, the grooves 6 are filled by doping boron by epitaxial growing method. Then, a P type diffused layer 7 is formed by heat treatment at a temperature higher than that at the time of epitaxial growth. The epitaxially grown layer Z' is removed. An N type Si single crystal 5'' is formed. The concentration of the gate which performs burial and the gate which contacts a layer of reverse conductivity type is reduced by epitaxial growth and heat treatment which follows it, thus enhancing the concentration at the center of the gate; therefore leakage current becomes small.
摘要翻译：目的：通过在外延生长后进行热处理的方法，通过增强栅极中心的浓度来防止通道闭合。构成：在N型基板上利用氧化膜2形成切槽6。接下来，通过外延生长法掺杂硼来填充槽6。然后，通过在高于外延生长时的温度下进行热处理形成P型扩散层7。除去外延生长层Z'。形成N型Si单晶5“。通过外延生长和随后的热处理来降低进行埋藏的栅极的浓度和与反向导电型层接触的栅极，从而提高栅极中心的浓度; 因此漏电流变小。

7. 发明专利

JPWO2010024243A1 バイポーラ型半導体装置およびその製造方法审中-公开
公开(公告)号：JPWO2010024243A1
公开(公告)日：2012-01-26
申请号：JP2010526714
申请日：2009-08-25
申请人：本田技研工業株式会社 , 新電元工業株式会社
发明人：佑樹根来 , 佑樹根来 , 明彦堀内 , 明彦堀内 , 健介岩永 , 健介岩永 , 誠一横山 , 誠一横山 , 英喜橋本 , 英喜橋本 , 賢一野中 , 賢一野中 , 雄介前山 , 雄介前山 , 雅佐藤 , 雅佐藤 , 清水　正章 , 正章清水
IPC分类号： H01L21/331 , H01L29/732 , H01L29/80 , H01L29/861
CPC分类号： H01L29/732 , H01L23/3171 , H01L23/3192 , H01L29/045 , H01L29/1608 , H01L29/42304 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66295 , H01L29/66416 , H01L29/7722 , H01L29/8613 , H01L2224/06181 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要：バイポーラ型トランジスタの表面準位密度を低減してその電流増幅率を高め、トランジスタ性能を向上することができるバイポーラ型半導体装置が開示される。バイポーラ型半導体装置(100)は、半導体素子の表面上に表面保護膜(30)を有する。該表面保護膜は、半導体素子の表面上に形成する熱酸化膜(31)と、熱酸化膜上に形成する堆積酸化膜(32)とからなる。該堆積酸化膜は水素元素と窒素元素のうち少なくともいずれか一方が1018cm−3以上含まれる。

8. 发明专利

JP2006093186A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006093186A
公开(公告)日：2006-04-06
申请号：JP2004272955
申请日：2004-09-21
申请人： Denso Corp , Hitachi Ltd , 株式会社デンソー , 株式会社日立製作所
发明人： OYANAGI TAKASUMI , WATANABE TOKUO , MALHAN RAJESH KUMAR , YAMAMOTO TAKESHI , MORISHITA TOSHIYUKI
IPC分类号： H01L29/80 , H01L21/28 , H01L21/337 , H01L29/808
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device such as JFET and SIT where low on-resistance is realized and high speed switching is possible.
SOLUTION: In JFET and SIT where current is turned on/off by a depletion layer extended to a channel between gate regions 13 formed along trench grooves 110 to 113, a gate contact layer 102 and a gate electrode 103, to which voltage can be supplied from outside, are installed on the surface of a semiconductor substrate or the base of the trench groove 113. Metal conductors (virtual gate electrodes) 101 which are ohmic-brought into contact with p
++ contact layers 14 of the gate regions 13 are arranged in bases of the trench grooves 110 to 112 that are independent of the gate contact layer 102 and the gate electrode 103. The virtual gate electrodes 101 are insulated from the gate electrode 103 and outer wiring. Thus, the silicon carbide semiconductor device can be obtained where gate resistance is made small and a high speed switching operation is possible.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供诸如JFET和SIT的碳化硅半导体器件，其中实现低导通电阻并且可以进行高速切换。解决方案：在JFET和SIT中，其中电流由延伸到沿沟槽110至113形成的栅极区域13之间的沟道的耗尽层导通/截止，栅极接触层102和栅极电极103，电压可以从外部供应，安装在半导体衬底的表面上或沟槽沟槽113的底部。金属导体（虚拟栅电极）101被欧姆接触到p ++ 栅极区域13的接触层14被布置在独立于栅极接触层102和栅电极103的沟槽110至112的基底中。虚拟栅电极101与栅极103和外部布线绝缘。因此，可以获得栅极电阻较小并且可以进行高速切换操作的碳化硅半导体器件。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JPS59108366A Manufacture of static induction transistor 失效
标题翻译：静电感应晶体管的制造
公开(公告)号：JPS59108366A
公开(公告)日：1984-06-22
申请号：JP21893082
申请日：1982-12-14
申请人： Fuji Photo Film Co Ltd , Junichi Nishizawa
发明人： NISHIZAWA JIYUNICHI , SUZUKI SOUBEE , IKEDA MITSURU , MUTOU HIDEKI
IPC分类号： H01L29/80 , H01L21/22 , H01L21/265 , H01L21/335 , H01L29/167 , H01L29/772 , H01L31/112
CPC分类号： H01L29/66416 , H01L21/26506 , H01L29/167 , H01L29/7722 , H01L31/1126
摘要： PURPOSE:To enable to perform thermal diffusion of impurities in the depth direction having anisotropy, and to obtain a vertical SIT formed deep in the thickness direction of the structure by a method wherein ions of an element lighter than a doping impurity element are implanted to different implanting depths of the plural number, and annealing is performed. CONSTITUTION:The III group element of B, Al, Ga, etc., for example, of impurities to act as an acceptor are doped to an n type layer 12 through thin SiO2 layer parts 26 at the parts corresponding to gate regions 16 and 18 or 20. Then, ions of an element lighter than the implanted impurities, B for example, are implanted in the parts corresponding to the gate regions 16 and 18 or 20 similarly. H or He is used for the light element thereof. Then, the whole of the structure implanted with the light element is annealed at a low temperature. As the annealing temperature, a comparatively low temperature of 500-1,200 deg.C is adopted, and desirably made to 700-900 deg.C.
摘要翻译：目的：为了能够在具有各向异性的深度方向上进行杂质的热扩散，并且通过以下方法获得深度在该结构的厚度方向上形成的垂直SIT，其中将比掺杂杂质元素更轻的元素的离子注入不同的注入多个深度，进行退火。构成：例如作为受体的杂质的B，Al，Ga等的III族元素在对应于栅极区域的部分通过薄SiO 2层部分26掺杂到n +型层12中 16和18或20.然后，类似地，将注入的杂质B的元素的离子B例如植入对应于栅极区域16和18或20的部分。 H或He用于其轻元素。然后，将植入光元件的整个结构在低温下退火。作为退火温度，采用500〜1200℃的较低温度，优选为700〜900℃。

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