专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP6407609B2 半導体装置の製造方法审中-公开
公开(公告)号：JP6407609B2
公开(公告)日：2018-10-17
申请号：JP2014158245
申请日：2014-08-01
申请人：ルネサスエレクトロニクス株式会社
发明人：川嶋祥之 , 茶木原啓 , 梅田恭子 , 西田彰男
IPC分类号： H01L27/11546 , H01L21/336 , H01L29/788 , H01L29/792 , H01L27/10 , H01L27/11573
CPC分类号： H01L27/1157 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L27/11529 , H01L27/11534 , H01L27/11573

2. 发明专利

JP6233829B2 半導体素子の製造方法有权
公开(公告)号：JP6233829B2
公开(公告)日：2017-11-22
申请号：JP2013008779
申请日：2013-01-21
申请人：エスケーハイニックス株式会社 , SK hynix Inc.
发明人：鄭愚 ▲徳▼ , 金成淳 , 宋柱一
IPC分类号： H01L21/768 , H01L23/532 , H01L21/336 , H01L29/788 , H01L29/792 , H01L21/3205 , H01L23/522 , H01L21/764 , H01L27/11521
CPC分类号： H01L21/764 , H01L27/11534

3. 发明专利

JP5726770B2 半導体装置及びその製造方法有权
公开(公告)号：JP5726770B2
公开(公告)日：2015-06-03
申请号：JP2012004082
申请日：2012-01-12
申请人：株式会社東芝
发明人：齋藤真澄 , 沼田敏典 , 佐久間究 , 草井悠
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/788 , H01L29/792 , H01L21/8244 , H01L27/11 , H01L27/10 , H01L27/105 , H01L27/08 , H01L21/8234 , H01L27/088 , H01L21/8238 , H01L27/092 , H01L29/786
CPC分类号： H01L29/78 , B82Y10/00 , H01L21/265 , H01L27/11534 , H01L27/11573 , H01L27/1203 , H01L27/1211 , H01L29/0653 , H01L29/1033 , H01L29/775 , H01L29/785 , H01L29/7881 , H01L29/792 , H01L29/0673 , H01L29/458

4. 发明专利

JP2013143536A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013143536A
公开(公告)日：2013-07-22
申请号：JP2012004082
申请日：2012-01-12
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO MASUMI , NUMATA TOSHINORI , SAKUMA KIWAMU , KUSAI HARUKA
IPC分类号： H01L29/786 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/78 , B82Y10/00 , H01L21/265 , H01L27/11534 , H01L27/11573 , H01L27/1203 , H01L27/1211 , H01L29/0653 , H01L29/0673 , H01L29/1033 , H01L29/458 , H01L29/775 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with improved characteristics without increasing occupied area and to provide a method of manufacturing the same.SOLUTION: There is provided a semiconductor device including a substrate having a primary surface and a first transistor provided on the primary surface. The first transistor includes a first stack, a first conductive part, a second conductive part, a first gate electrode, and a first gate insulating film. The first stack includes a plurality of first semiconductor layers and a plurality of first insulating layers that are alternately stacked in a first direction perpendicular to the primary surface. The first conductive part is electrically connected to some of the first semiconductor layers of the plurality of first semiconductor layers. The second conductive part is spaced apart from the first conductive part in a second direction perpendicular to the first direction, and is electrically connected to at least some of the first semiconductor layers. The first gate electrode is located between the first conductive part and the second conductive part, and is faced to side surfaces of the plurality of first semiconductor layers. The first gate insulating film is located between the first gate electrode and the first semiconductor layers.
摘要翻译：要解决的问题：提供具有改进的特性而不增加占用面积的半导体器件，并提供其制造方法。解决方案：提供一种半导体器件，其包括具有主表面的衬底和设置在主要表面上的第一晶体管表面。第一晶体管包括第一堆叠，第一导电部分，第二导电部分，第一栅极电极和第一栅极绝缘膜。第一堆叠包括沿垂直于主表面的第一方向交替堆叠的多个第一半导体层和多个第一绝缘层。第一导电部分电连接到多个第一半导体层中的一些第一半导体层。第二导电部分在垂直于第一方向的第二方向上与第一导电部分间隔开，并且电连接到至少一些第一半导体层。第一栅电极位于第一导电部和第二导电部之间，并且面对多个第一半导体层的侧面。第一栅极绝缘膜位于第一栅电极和第一半导体层之间。

5. 发明专利

JP5216360B2 Semiconductor device 有权
公开(公告)号：JP5216360B2
公开(公告)日：2013-06-19
申请号：JP2008036771
申请日：2008-02-19
申请人：株式会社半導体エネルギー研究所
发明人：舜平山崎 , 郁子川俣 , 康行荒井
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/08 , H01L27/10 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L27/11546 , H01L27/1203 , H01L27/1214 , H01L29/66825 , H01L29/7881
摘要： Plural kinds of thin film transistors having different film thicknesses of semiconductor layers are provided over a substrate having an insulating surface. A channel formation region of semiconductor layer in a thin film transistor for which high speed operation is required is made thinner than a channel formation region of a semiconductor layer of a thin film transistor for which high withstand voltage is required. A gate insulating layer of the thin film transistor for which high speed operation is required may be thinner than a gate insulating layer of the thin film transistor for which high withstand voltage is required.

6. 发明专利

JP5045105B2 Non-volatile semiconductor memory device, a method of driving the same and a method of manufacturing the same 有权
公开(公告)号：JP5045105B2
公开(公告)日：2012-10-10
申请号：JP2006545103
申请日：2005-11-16
申请人：日本電気株式会社
发明人：啓仁渡辺 , 潤砂村 , 哲史西藤
IPC分类号： H01L29/792 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11534 , G11C16/0408 , G11C16/0416 , G11C16/10 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L29/42324 , H01L29/66825

7. 发明专利

JP4669655B2 Method of manufacturing a semiconductor memory device 有权
公开(公告)号：JP4669655B2
公开(公告)日：2011-04-13
申请号：JP2003198260
申请日：2003-07-17
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：洪善梁 , 魯烈郭
IPC分类号： H01L27/10 , H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： Disclosed is a method of manufacturing a semiconductor memory device. An ion implantation layer is formed into a given depth of the semiconductor substrate. Therefore, it is possible to prevent the dopant (P31) gettered on the surface of the semiconductor substrate from being diffused toward the bottom when a well ion is injected. The dopant (P31) gettered on the surface of the semiconductor substrate is easily experienced by transit-enhanced diffusion even at low temperature. Also, the dopant may serve as counter dopping in the buried channel. In the present invention, as the behavior of this dopant (P31) is prohibited in a subsequent annealing process, the concentration of the ion for controlling the threshold voltage could be uniformly kept. Therefore, the present invention can manufacture devices of high reliability having a stable threshold voltage characteristic and can be flexibly applied to manufacturing the devices depending on reduction in the design rule.

8. 发明专利

JP2006310562A Semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2006310562A
公开(公告)日：2006-11-09
申请号：JP2005131593
申请日：2005-04-28
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： KUBOYAMA KENICHI , KANAMORI KOJI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0433 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11534 , H01L29/42328 , H01L29/7885
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing the off-leak derived from miniaturization of a memory cell, and to provide its manufacturing method. SOLUTION: One unit cell comprises a substrate 1 which has a trench 1a a selection gate 3 allocated via an insulating film 2 on the substrate 1 which adjoins the trench 1a, a first well 1b provided in the substrate 1 surface under the selection gate 3, a floating gate 6 allocated in the bottom or on the side wall surface of the trench 1a via an insulating film 8a, a second well 1c provided in the trench 1a bottom surface under the floating gate 6, a first diffusion region 7a established in the trench 1a bottom surface, and a control gate 11 allocated via the insulating film 8 on the floating gate 6. The side wall surface of the trench 1a or the vicinity of the bottom with a respect to a selection gate 3 is used as a channel so that the impurity concentration of the first well 1b is below the impurity concentration of the second well 1c. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够减少由于存储单元的小型化导致的泄漏的半导体存储器件，并提供其制造方法。解决方案：一个单元包括衬底1，衬底1具有通过绝缘膜2分配的选择栅极3的沟槽1a，衬底1上邻接沟槽1a，第一阱1b设置在衬底1表面的选择下栅极3，经由绝缘膜8a分配在沟槽1a的底部或侧壁表面的浮动栅极6，设置在浮动栅极6下方的沟槽1a底表面中的第二阱1c，建立第一扩散区域7a 在沟槽1a底表面中，以及通过绝缘膜8在浮动栅极6上分配的控制栅极11.沟槽1a的侧壁表面或相对于选择栅极3的底部附近被用作使得第一阱1b的杂质浓度低于第二阱1c的杂质浓度。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006295180A Field-effect transistor having perpendicular electrode and manufacturing method thereof 审中-公开
标题翻译：具有普通电极的场效应晶体管及其制造方法
公开(公告)号：JP2006295180A
公开(公告)日：2006-10-26
申请号：JP2006107587
申请日：2006-04-10
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM SUNG-MIN , PARK DONG-GUN , KIN DOUIN , KIM MIN-SANG , YUN EUN-JUNG
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/08 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L27/11534 , H01L27/1203 , H01L29/42336 , H01L29/66621 , H01L29/66795 , H01L29/7851 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a field-effect transistor having a perpendicular electrode and a manufacturing method thereof. SOLUTION: A planar memory device and vertically oriented thin body devices are formed on a common semiconductor layer in a semiconductor device and a manufacturing method of the semiconductor device. For example, it is desirable that a memory device has a planar transistor in a surrounding region around the device and the vertically oriented thin body transistors in the cell region of the device. This allows the merits in each form of the device to be applied to each suitable function of the memory device. COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2005072563A Method of forming gate oxide film for semiconductor device 有权
标题翻译：形成半导体器件的栅极氧化膜的方法
公开(公告)号：JP2005072563A
公开(公告)日：2005-03-17
申请号：JP2004191040
申请日：2004-06-29
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： RI MINKEI , CHANG HEE HYUN , KIN SENJU , AHN JUNG RYUL
IPC分类号： H01L21/336 , H01L21/316 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/11534 , Y10S438/981
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a gate oxide film for a semiconductor device, which can minimize the difference in surface level between a high-voltage gate oxide film, formed at a high-voltage transistor and a low-voltage gate oxide film formed at a low-voltage transistor.
SOLUTION: The method comprises the steps of sequentially forming a pad oxide film and a pad nitride film at an upper part of a semiconductor substrate, in which a low-voltage region for forming the low-voltage transistor and a high-voltage region for forming the high-voltage transistor are defined; allowing the high-voltage region to expose and patterning the resultant so that a predetermined region of the high-voltage region of the semiconductor substrate is recessed; removing a first gate oxide film at the exposed high-voltage region; removing the first gate oxide film; forming a second gate oxide film at the high-voltage region from which the first gate oxide film has been removed; removing the pad nitride film and the pad oxide film formed in the preceding step, and effecting etching so that the second gate oxide film at the high-voltage region is recessed by a predetermined depth; and forming a third gate oxide film throughout the surface of the resultant from the preceding step.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种形成用于半导体器件的栅极氧化膜的方法，其可以使形成在高压晶体管的高电压栅氧化膜与低电压晶体管之间的表面电平差异最小化电压栅氧化膜形成在低压晶体管。解决方案：该方法包括以下步骤：在半导体衬底的上部依次形成衬垫氧化膜和衬垫氮化物膜，其中用于形成低压晶体管的低电压区域和高电压定义形成高压晶体管的区域; 允许高电压区域暴露和图案化所得的结果，使得半导体衬底的高电压区域的预定区域凹陷; 在暴露的高压区域去除第一栅极氧化膜; 去除第一栅氧化膜; 在去除所述第一栅极氧化膜的高电压区域形成第二栅极氧化膜; 去除在前一步骤中形成的衬垫氮化物膜和衬垫氧化膜，并进行蚀刻，使得高电压区域处的第二栅极氧化膜凹陷预定深度; 以及在前一步骤的结果的整个表面上形成第三栅极氧化物膜。版权所有（C）2005，JPO＆NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式