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    • 1. 发明专利
    • Electromechanical memory device and fabrication method thereof
    • 电子存储器件及其制造方法
    • JP2008047901A
    • 2008-02-28
    • JP2007206449
    • 2007-08-08
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • YUN EUN-JUNGRI SEIEIKIM MIN-SANGKIM SUNG-MIN
    • H01L27/10B81B3/00B81C1/00G11C11/21
    • PROBLEM TO BE SOLVED: To provide a memory device with high reliability and good operation characteristics and a method for fabrication thereof. SOLUTION: A memory device comprises a substrate 100, a first electrode 110 which is extended vertically for the substrate 100, and a second electrode 120 which is extended vertically for the substrate 100 and is separated from the first electrode 110 with an electrode gap. In addition, the memory device comprises a third electrode which is extended vertically to the inside of the electrode gap and is separated from the first electrode 110 with a first gap 118A and from the second electrode 120 with a second gap 118B to allow electrostatic deformation in a way that the first bend state enables electric connection to the first electrode 110 via the first gap 118A, the second bend state enables electric connection to the second electrode 120 via the second gap 118B and the standby state enables electric isolation from the first electrode 110 and second electrode 120. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供具有高可靠性和良好操作特性的存储器件及其制造方法。 解决方案:存储器件包括衬底100,垂直于衬底100延伸的第一电极110和垂直延伸用于衬底100的第二电极120,并与第一电极110与电极分离 间隙。 此外,存储器件包括第三电极,其垂直于电极间隙的内部延伸并且与第一电极110分离,具有第一间隙118A,并且与第二电极120与第二间隙118B分离,以允许静电变形 第一弯曲状态能够经由第一间隙118A与第一电极110电连接的方式,第二弯曲状态使得能够经由第二间隙118B与第二电极120电连接,并且待机状态使得能够从第一电极110电隔离 和第二电极120.版权所有(C)2008,JPO&INPIT
    • 3. 发明专利
    • Memory element, and manufacturing method thereof
    • 记忆元件及其制造方法
    • JP2008042206A
    • 2008-02-21
    • JP2007202739
    • 2007-08-03
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • YUN EUN-JUNGRI SEIEIRO KYOKANKIM MIN-SANGKIM SUNG-MIN
    • H01L21/8247H01L27/115H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To provide a memory element having a laminated structure, and to provide a method for manufacturing the memory element.
      SOLUTION: The memory element 101 includes a first active region 105 on a substrate 100, and first and second source/drain regions 150, 152 positioned on the substrate adjacent to the first and second sidewalls of the first active region 105. A first gate structure 132 is arranged on the first active region 105 between the first and second source/drain regions 150, 152. There is a second active region 104a positioned on the first gate structure 132 at a part that is between and adjacent to the first and second source/drain 150, 152. A second gate structure 148 is arranged on the second active region 104a positioned on the first gate structure 132.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种具有层压结构的存储元件,并提供一种用于制造存储元件的方法。 存储元件101包括衬底100上的第一有源区105以及与第一有源区105的第一和第二侧壁相邻的位于衬底上的第一和第二源/漏区150,152。 第一栅极结构132布置在第一和第二源极/漏极区域150,152之间的第一有源区域105上。在第一栅极结构132和第二栅极结构132之间的第一和第二源极/漏极区域150,152之间的部分处设置有第二有源区域104a。 第二栅极/漏极150,152。第二栅极结构148布置在位于第一栅极结构132上的第二有源区域104a上。(C)2008,JPO和INPIT
    • 8. 发明专利
    • Transistor, and manufacturing method thereof
    • 晶体管及其制造方法
    • JP2008042209A
    • 2008-02-21
    • JP2007204374
    • 2007-08-06
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • YUN EUN-JUNGRI SEIEIKIM MIN-SANGKIM SUNG-MINJO HYE-JIN
    • H01L21/8247H01L27/115H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To provide a transistor for non-volatile memory devices that has a vertical laminated structure and can achieve high integration effectively, and to provide a method for manufacturing the transistor.
      SOLUTION: The transistor 100 used as a vertical twin-channel transistor includes: pairs 115, 116 of first and second vertical overlap source and drain positioned on a substrate 101; first and second vertical channel regions 117 extended between the pairs 115, 116 of first and second vertical overlap source and drain; first and second insulating regions 109, 112 positioned while being adjacent to the first and second vertical channel regions 117 between the first and second vertical overlap source/drain regions 115, 116; first and second gate insulators 110 including a charge trap film formed on the first and second vertical channel regions 117; and a gate electrode 111 formed between the first and second insulators 110.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种具有垂直层压结构并可以有效实现高集成度的非易失性存储器件的晶体管,并提供一种用于制造晶体管的方法。 用作垂直双通道晶体管的晶体管100包括:位于衬底101上的第一和第二垂直重叠源极和漏极的对115,116; 在第一和第二垂直重叠源和漏极的对115,116之间延伸的第一和第二垂直沟道区域117; 第一和第二绝缘区域109,112位于第一和第二垂直重叠源极/漏极区域115,116之间,与第一和第二垂直沟道区域117相邻; 包括形成在第一和第二垂直沟道区域117上的电荷陷阱膜的第一和第二栅极绝缘体110; 以及形成在第一和第二绝缘体110之间的栅极电极111.权利要求:(C)2008,JPO&INPIT