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1. 发明专利

JP2014096466A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014096466A
公开(公告)日：2014-05-22
申请号：JP2012246969
申请日：2012-11-09
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc. , Tohoku Univ , 国立大学法人東北大学
发明人： SEO MOON-SIK , ENDO TETSUO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11556 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/7889
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device appropriate for reducing interference between stacked floating gates; and provide a manufacturing method of the semiconductor device.SOLUTION: A device comprises: a channel film CH which projects from a substrate SUB and has projections P on side walls; floating gates FG which surround the channel film CH and each is formed between the projections P; control gates CG which surround the floating gates FG and which are stacked along the channel film CH; and interlayer insulation films 13 each sandwiched between the stacked control gates CG. A lateral face of the floating gate FG and a lateral face of the projection P have a level difference k.
摘要翻译：要解决的问题：提供适合于减少堆叠浮动栅极之间的干扰的半导体器件; 并提供半导体器件的制造方法。解决方案：一种器件包括：从衬底SUB突出并在侧壁上具有突起P的沟道膜CH; 围绕通道膜CH并且分别形成在突起P之间的浮栅FG; 围绕浮动栅极FG并且沿着沟道膜CH堆叠的控制栅极CG; 以及夹在堆叠的控制栅极CG之间的层间绝缘膜13。浮栅FG的侧面和突起P的侧面具有电平差k。

2. 发明专利

JP2014049747A Semiconductor device including tungsten gate electrode and method for manufacturing the same 有权
标题翻译：包含钨氢电极的半导体器件及其制造方法
公开(公告)号：JP2014049747A
公开(公告)日：2014-03-17
申请号：JP2013006888
申请日：2013-01-18
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： KANG DONG-KYUN
IPC分类号： H01L21/8238 , C23C16/08 , C23C16/18 , H01L21/28 , H01L21/285 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823857 , H01L27/092 , H01L29/401 , H01L29/4966
摘要： PROBLEM TO BE SOLVED: To provide: a semiconductor device in which a threshold voltage of an NMOS and a threshold voltage of a PMOS can be independently adjusted; and a method for manufacturing the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming carbon-containing tungsten 24N in an NMOS region on a gate insulating film 23 formed on the whole face of a semiconductor substrate 21; forming a carbon-containing tungsten nitride 26P in a PMOS region; forming tungsten films 27N and 27P on the carbon-containing tungsten 24N and on the carbon-containing tungsten nitride 26P, respectively; performing post-heat treatment; and etching the tungsten films 27N and 27P, the carbon-containing tungsten 24N and the carbon-containing tungsten nitride 26P to form a first gate electrode 201 and a second gate electrode 202. By utilizing a tungsten-containing film containing a work function adjustment material, a double metal gate electrode having a work function suitable for each transistor and low resistance can be formed.
摘要翻译：要解决的问题：提供：可以独立地调整NMOS的阈值电压和PMOS的阈值电压的半导体器件; 以及半导体器件的制造方法。解决方案：一种半导体器件的制造方法，包括以下步骤：在形成在半导体衬底21的整个面上的栅极绝缘膜23上的NMOS区域中形成含碳钨24N; 在PMOS区中形成含碳的氮化钨26P; 分别在含碳钨24N和含碳氮化钨26P上形成钨膜27N和27P; 进行后热处理; 并且蚀刻钨膜27N和27P，含碳钨24N和含碳氮化钨26P以形成第一栅电极201和第二栅电极202.通过使用含有功函数调节材料的含钨膜可以形成具有适合于每个晶体管的功函数和低电阻的双金属栅电极。

3. 发明专利

JP2013165266A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013165266A
公开(公告)日：2013-08-22
申请号：JP2013004859
申请日：2013-01-15
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： LEE KI-HONG , PYI SEUNG HO , SOHN HYUN-SOO
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/32133 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same which are suitable to reduce height of a multilayer film and to increase the degree of integration in a memory element.SOLUTION: A semiconductor device includes: a plurality of word lines and a plurality of interlayer insulating films alternately stacked over a substrate; a plurality of vertical channel films protruding from the substrate and passing through the plurality of word lines and the plurality of interlayer insulating films; a tunnel insulating film surrounding the plurality of vertical channel films; a charge trap layer surrounding the tunnel insulating film, where first regions between the tunnel insulating film and the word lines have thickness smaller than thickness of second regions between the tunnel insulating film and the interlayer insulating films; and first charge blocking film patterns surrounding the first regions of the charge trap layer.
摘要翻译：要解决的问题：提供适合于降低多层膜的高度并增加存储元件的集成度的半导体器件及其制造方法。解决方案：半导体器件包括：多个字线和多个交替层叠在基板上的层间绝缘膜; 从所述基板突出并穿过所述多个字线和所述多个层间绝缘膜的多个垂直沟道膜; 围绕所述多个垂直通道膜的隧道绝缘膜; 围绕隧道绝缘膜的电荷陷阱层，隧道绝缘膜和字线之间的第一区域的厚度小于隧道绝缘膜和层间绝缘膜之间的第二区域的厚度; 以及围绕电荷陷阱层的第一区域的第一电荷阻挡膜图案。

4. 发明专利

JP2013125967A Semiconductor element and manufacturing method of the same 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：JP2013125967A
公开(公告)日：2013-06-24
申请号：JP2012270395
申请日：2012-12-11
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： AHN JUNG RYUL , LI RUN JING
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11565 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and a manufacturing method of the same, which can form a pattern having a width finer than resolution of exposure equipment and which can form patterns at finer intervals.SOLUTION: A semiconductor element comprises: a plurality of first trenches formed on a semiconductor substrate and each having a first depth; a plurality of second trenches formed on the semiconductor substrate among the plurality of first trenches and each having a second depth different from the first depth; a plurality of element isolation films formed on the plurality of first trenches and the plurality of second trenches and each having a protrusion with an upper part protruding higher than the semiconductor substrate; and a plurality of memory cells formed on the semiconductor substrate among the plurality of element isolation films.
摘要翻译：要解决的问题：为了提供一种半导体元件及其制造方法，其可以形成具有比曝光设备的分辨率更窄的宽度的图案，并且可以以更精细的间隔形成图案。解决方案：半导体元件包括：多个第一沟槽，形成在半导体衬底上，并且每个具有第一深度; 多个第二沟槽，形成在所述多个第一沟槽中的所述半导体衬底上，并且每个具有不同于所述第一深度的第二深度; 形成在所述多个第一沟槽和所述多个第二沟槽上的多个元件隔离膜，并且每个具有突起高于半导体衬底的上部突起; 以及形成在所述多个元件隔离膜中的所述半导体衬底上的多个存储单元。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2013125577A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2013125577A
公开(公告)日：2013-06-24
申请号：JP2012264987
申请日：2012-12-04
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： GYU NAM YIM , WOON JU CHANG
IPC分类号： G11C11/4091 , G11C11/401
CPC分类号： G11C7/08 , G11C7/065 , G11C7/12 , G11C29/12 , G11C2029/1204
摘要： PROBLEM TO BE SOLVED: To provide a bit line sense amplifier having improved low-voltage characteristics.SOLUTION: A semiconductor memory device according to one aspect of the present invention includes a first sense amplifier part which is driven by a power drive signal and a ground drive signal and has a first inverter and a second inverter connected to each other in a latch structure between a bit line and a bit line bar, and a second sense amplifier part which is driven by the ground drive signal and has a first transistor and a second transistor connected to each other in a latch structure between the bit line and the bit line bar when a switching signal that has been made active is applied thereto. A threshold voltage of the second sense amplifier part is set to be lower than that of the first sense amplifier part.
摘要翻译：要解决的问题：提供具有改进的低电压特性的位线读出放大器。解决方案：根据本发明的一个方面的半导体存储器件包括由功率驱动信号和接地驱动信号驱动的第一读出放大器部分，并且具有彼此连接的第一反相器和第二反相器在位线和位线条之间的锁存结构，以及第二读出放大器部分，其由接地驱动信号驱动，并且具有第一晶体管和第二晶体管，其位于位线和位线之间的锁存结构中当已经被激活的切换信号被施加到位线条时。第二读出放大器部分的阈值电压被设置为低于第一读出放大器部分的阈值电压。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2013114736A Semiconductor memory device, set program control circuit and program method therefor 审中-公开
标题翻译：半导体存储器件，设置程序控制电路及其程序方法
公开(公告)号：JP2013114736A
公开(公告)日：2013-06-10
申请号：JP2012127159
申请日：2012-06-04
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： AHN YEON BOK
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C13/0097
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of programming set data in response to an erasure instruction, a set program control circuit and program method therefor.SOLUTION: A semiconductor memory device of the present invention comprises: a program pulse generation section that generates, in response to a programming enable signal, a first write control signal, a second write control signal, and a program completion signal; a set program control circuit that repeatedly generates, in response to an erasure instruction and the program completion signal, a set programming enable signal for the specified number of times; and a controller that disables, in response to the erasure instruction, the first write control signal and generates, in response to the set programming enable signal, a programming enable signal.
摘要翻译：解决的问题：提供能够响应于擦除指令编程设置数据的半导体存储器件，设置的程序控制电路及其程序方法。解决方案：本发明的半导体存储器件包括：编程脉冲产生部分，响应于编程使能信号产生第一写控制信号，第二写控制信号和程序完成信号; 设置程序控制电路，响应于擦除指令和程序完成信号，反复产生设定的编程使能信号指定次数; 以及控制器，其响应于擦除指令而禁用第一写入控制信号，并且响应于所设置的编程使能信号而产生编程使能信号。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2013101737A Address decoding method and semiconductor memory device using the same 审中-公开
标题翻译：使用该方法的地址解码方法和半导体存储器件
公开(公告)号：JP2013101737A
公开(公告)日：2013-05-23
申请号：JP2012101455
申请日：2012-04-26
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： CHU SHIN HO
IPC分类号： G11C11/4076 , G11C11/401 , G11C11/408
CPC分类号： G11C8/18 , G11C29/1201 , G11C29/12015 , G11C29/18
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing failures of reading operation and writing operation of a semiconductor memory device.SOLUTION: The semiconductor memory device includes: a strobe clock generating section 10 for generating a strobe clock of which a delay amount is adjusted according to a first test mode signal to a third test mode signal that are selectively enabled in response to a reading signal or a writing signal; an internal address generating section 20 for latching an address in response to a first level of the strobe block, decoding the address in response to a second level of the strobe block, and generating an internal address; and an output enable signal generating section 30 for decoding the internal address, and generating an output enable signal which is selectively enabled.
摘要翻译：解决的问题：提供能够防止半导体存储器件的读取操作和写入操作失败的半导体存储器件。解决方案：半导体存储器件包括：选通时钟产生部分10，用于产生根据第一测试模式信号将延迟量调整到第三测试模式信号的选通时钟，该第三测试模式信号响应于第三测试模式信号选择性地使能读取信号或写入信号; 内部地址生成部分20，用于响应于选通块的第一电平来锁存地址，响应于选通块的第二电平对该地址进行解码，并产生一个内部地址; 以及用于对内部地址进行解码的输出使能信号生成部30，并且生成有选择地使能的输出使能信号。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2013097852A Semiconductor memory device and test circuit for the same 审中-公开
标题翻译：半导体存储器件及其测试电路
公开(公告)号：JP2013097852A
公开(公告)日：2013-05-20
申请号：JP2012024875
申请日：2012-02-08
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： LEE JAEEUN
IPC分类号： G11C29/12 , G01R31/28
CPC分类号： G11C29/1201 , G11C29/48
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving a test speed, and to provide a test circuit for the same.SOLUTION: The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a switching portion which is connected to a data input/output pad, and controls a transmission path of data having been applied to the data input/output pad in response to a test mode signal; a write driver which drives the data transmitted from the switching portion, and writes the driven data into the memory cell array, in a normal mode; and a controller which transmits the data transmitted from the switching portion to the memory cell in a test mode.
摘要翻译：要解决的问题：提供能够提高测试速度的半导体存储器件，并提供用于其的测试电路。解决方案：半导体存储器件包括：包括多个存储单元的存储单元阵列; 切换部分，其连接到数据输入/输出焊盘，并且响应于测试模式信号控制已经被施加到数据输入/输出焊盘的数据的传输路径; 写入驱动器，其驱动从切换部分发送的数据，并将驱动数据以正常模式写入存储单元阵列; 以及控制器，其以测试模式将从切换部分发送的数据发送到存储器单元。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2013089952A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013089952A
公开(公告)日：2013-05-13
申请号：JP2012158275
申请日：2012-07-17
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： SAN HUN-JIN , LEE DONGWOOK
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/02372 , H01L2224/02381 , H01L2224/0401 , H01L2224/05008 , H01L2224/05548 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including various connection structures of through vias formed in laminated chips.SOLUTION: A semiconductor device comprises: laminated first and second chips; first through third through vias each positioned on the same line perpendicular to the first and second chips and formed to penetrate the first and second chips; and a first input/output circuit connected to the second through via of the first chip and a second input/output circuit connected to the second through via of the second chip.

10. 发明专利

JP2013078129A Frequency adjusting apparatus and dll circuit including the same 审中-公开
标题翻译：频率调整装置和DLL电路，包括它们
公开(公告)号：JP2013078129A
公开(公告)日：2013-04-25
申请号：JP2012262223
申请日：2012-11-30
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： CHO KOSHUN , CHUN JUN HYUN
IPC分类号： H03L7/081 , H03K5/135
CPC分类号： H03L7/0814
摘要： PROBLEM TO BE SOLVED: To provide a frequency adjusting apparatus for reducing electromagnetic interference of a semiconductor integrated circuit, and to provide a DLL circuit including the frequency adjusting apparatus.SOLUTION: A frequency adjusting apparatus of the present invention comprises: a frequency control signal generating section for generating a frequency control signal with a plurality of bits by dividing a frequency of a reference clock in a plurality of frequency dividing ratios; and a frequency adjusting section for adjusting the frequency of the inputted reference clock in response to the frequency control signal with the plurality of bits.

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