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1. 发明专利

JP6195342B2 情報処理装置およびメモリアクセス制御方法有权
公开(公告)号：JP6195342B2
公开(公告)日：2017-09-13
申请号：JP2013067126
申请日：2013-03-27
申请人：キヤノン株式会社
发明人：本條智也 , 山本貴久
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0607 , G06F12/0623

2. 发明专利

JP5481823B2 Memory modules, and auxiliary modules for memory 有权
公开(公告)号：JP5481823B2
公开(公告)日：2014-04-23
申请号：JP2008261521
申请日：2008-10-08
申请人：株式会社バッファロー
发明人：香湯浅
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G06F12/0623

3. 发明专利

JP2013205872A Storage control apparatus, storage apparatus, information processing system, and processing method therein 审中-公开
标题翻译：存储控制装置，存储装置，信息处理系统及其处理方法
公开(公告)号：JP2013205872A
公开(公告)日：2013-10-07
申请号：JP2012070830
申请日：2012-03-27
申请人： Sony Corp , ソニー株式会社
发明人： NAKANISHI KENICHI , TSUTSUI KEIICHI , FUJINAMI YASUSHI , ADACHI NAOHIRO , ISHII TAKESHI , OKUBO HIDEAKI , SHINBASHI TATSUO
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G06F12/0623 , G06F12/06 , G06F12/0607
摘要： PROBLEM TO BE SOLVED: To shorten specification of an address when requesting access to a plurality of access units in a memory space composed of a plurality of banks.SOLUTION: A command processing section receives a command requesting access to a plurality of access units by specifying one address in a memory space composed of a plurality of banks. An address generating section generates an address of an access unit which is an object of the access in a bank predetermined for the specified address among the plurality of banks.
摘要翻译：要解决的问题：在请求访问由多个存储体组成的存储空间中的多个访问单元时，缩短地址的规范。解决方案：命令处理部分通过指定请求访问多个访问单元来接收请求由多个银行组成的存储空间中的一个地址。地址产生部分生成作为多个银行中指定的地址预定的存储体中的访问对象的访问单元的地址。

4. 发明专利

JP2012238341A Daisy-chain cascade devices 审中-公开
标题翻译： DAISY-CHAIN CASCADE设备
公开(公告)号：JP2012238341A
公开(公告)日：2012-12-06
申请号：JP2012198200
申请日：2012-09-10
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , KIM JIN-KI , OH HAK JUNE
IPC分类号： G06F13/37 , G06F1/10
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To serially couple devices in a daisy-chain cascading arrangement.SOLUTION: Devices are coupled to a daisy-chain cascading arrangement such that an output unit of a first device is coupled to an input unit of a second device located behind the daisy-chain cascade to accommodate the transfer of information, such as data, an address and command information, and control signals to the second device from the first device. The device coupled in the daisy-chain comprise a serial input unit SI and a serial output unit SO. Information is input to the device via the SI. The information is output from the device via the SO. The SO of the device located in front of the daisy-chain cascade is coupled to the SI of the device located behind the daisy-chain cascade. The information input to the forward device via the SI is output via the SO of the device. The information is then transferred to the SI of the rearward device.
摘要翻译：要解决的问题：串联菊花链级联布置中的设备。解决方案：设备耦合到菊花链级联布置，使得第一设备的输出单元耦合到位于菊花链级联背后的第二设备的输入单元，以适应信息的传送，例如数据，地址和命令信息，以及从第一设备到第二设备的控制信号。耦合在菊花链中的装置包括串行输入单元SI和串行输出单元SO。信息通过SI输入到设备。信息通过SO从设备输出。位于菊花链级联前面的器件的SO耦合到位于菊花链级联后面的器件的SI。通过SI输入到正向设备的信息通过设备的SO输出。然后将信息传送到后方装置的SI。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP4988082B2 Microprocessor and data processing system 有权
公开(公告)号：JP4988082B2
公开(公告)日：2012-08-01
申请号：JP2000147111
申请日：2000-05-18
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：鍾根安
IPC分类号： G06F9/32 , G06F12/06 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/40 , G06F9/48 , G06F12/02
CPC分类号： G06F9/342 , G06F9/30181 , G06F12/0292 , G06F12/0623

6. 发明专利

JP3375669B2 I / o memory card of the access method and the method of its operation 失效
公开(公告)号：JP3375669B2
公开(公告)日：2003-02-10
申请号：JP6355293
申请日：1993-03-23
申请人：富士通株式会社
发明人：康祐新井
IPC分类号： G06F13/00 , G06F12/06 , G06F13/12 , G06F13/14 , G06F13/38 , G06K7/00 , G06K19/07 , G07F7/10 , G11C5/00
CPC分类号： G06Q20/341 , G06F12/0623 , G06F12/0646 , G06F13/128 , G06F13/387 , G06K7/0008 , G06Q20/3576 , G07F7/1008

7. 发明专利

JPS5781663A Auxiliary storage device 失效
标题翻译：辅助存储设备
公开(公告)号：JPS5781663A
公开(公告)日：1982-05-21
申请号：JP15699780
申请日：1980-11-10
申请人： Toshiba Corp
发明人： FURUYA AKIHIKO
IPC分类号： G11B27/10 , G06F3/06 , G06F12/06
CPC分类号： G06F12/0623
摘要： PURPOSE:To increase a data storage area without increasing the capacity of the whole device, by adopting such a storage system as provides one address part on one block consisting of plural data sectors. CONSTITUTION:Each block 0-3 of an auxiliary storage device consists of plural sectors (4 sectors), and address parts AD0-AD3 are provided on each block 0-3, respectively. In this state, upper bits of an address are assigned to the block and lower bits of the address are assigned to the sector. An address 2 containing a prescribed sector 22 is outputted from an access device of the auxiliary storage device. In accordance with this address, when an address AD1 being nearest to the AD2 of the block 2 has been detected, the lower bit of the address is outputted to a decoder 106, and a signal 109 for designating a prescribed sector is outputted. At the same time, a pseudo gate singal generating circuit 104 outputs its signal, and a gate singal for accessing the data sector 22 is outputted from an AND113.
摘要翻译：目的：通过采用这样的存储系统，在不增加整个设备的容量的情况下增加数据存储区域，在由多个数据扇区组成的一个块上提供一个地址部分。构成：辅助存储装置的每个块0-3由多个扇区（4个扇区）组成，并且分别在每个块0-3上提供地址部分AD0-AD3。在这种状态下，将地址的高位分配给块，并将该地址的低位分配给扇区。包含规定扇区22的地址2从辅助存储装置的存取装置输出。根据该地址，当检测到最接近块2的AD2的地址AD1时，地址的低位被输出到解码器106，并输出指定规定扇区的信号109。同时，伪门信号发生电路104输出其信号，并且从AND113输出用于访问数据扇区22的门信号。

8. 发明专利

JPS5716427B2 JPS5716427B2 - 失效
公开(公告)号：JPS5716427B2
公开(公告)日：1982-04-05
申请号：JP13228776
申请日：1976-11-02
IPC分类号： G06F12/06 , G11C11/415 , G11C17/00 , G11C17/12
CPC分类号： G11C11/415 , G06F12/0623 , G11C17/12

9. 发明专利

JPS5750060A Memory controlling circuit 失效
标题翻译：内存控制电路
公开(公告)号：JPS5750060A
公开(公告)日：1982-03-24
申请号：JP12578480
申请日：1980-09-10
申请人： Toshiba Corp
发明人： AOYANAGI KEIZOU
IPC分类号： G06F9/34 , G06F12/04 , G06F12/06
CPC分类号： G06F12/0623
摘要： PURPOSE:To execute a memory access exceeding a boundary of a memory address, by means of a few hardware and also at a high speed. CONSTITUTION:In a processing equipment provided with a memory by which an address is assigned in a byte unit, and a memory access is executed in a unit >=2 bytes, a memory address register inputs an end signal END1 to an AND gate 12 when the first memory cycle ends. It is discriminated by the AND gate12 that the memory access exceeds the address boundary. When an output of the gate12 become ''1'', an FF13 is set, the memory starts the second memory cycle by a memory starting circuit 15. According to this constitution, contents of the memory address register are returned to its initial value at a high speed without requiring a subtracter, etc., and also without executing a subtraction processing by a microprogram.
摘要翻译：目的：通过一些硬件和高速执行超出存储器地址边界的存储器访问。构成：在具有通过字节单位分配地址的存储器的处理设备中，以> = 2字节为单位执行存储器访问，存储器地址寄存器将结束信号END1输入到与门12，当第一个内存循环结束。与门12鉴别存储器访问超过地址边界。当门12的输出变为“1”时，设置FF13，存储器启动电路15开始第二存储周期。根据该结构，存储器地址寄存器的内容返回到其初始值高速而不需要减法器等，并且也不执行微程序的减法处理。

10. 发明专利

JPS5730060A Address space expansion system 失效
标题翻译：地址扩展系统
公开(公告)号：JPS5730060A
公开(公告)日：1982-02-18
申请号：JP10433580
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： AZUMA MASAYUKI , IURA AKIHIKO
IPC分类号： G06F13/16 , G06F12/06 , G06F15/78
CPC分类号： G06F12/0623
摘要： PURPOSE:To provide many memory devices, by converting a part of data bit into address bit through the use of address and data buses with a certain line number. CONSTITUTION:A microprocessor 11 is connected to memory package 23 and a display device 19 with an address bus 12 and a data bus 13. The memory package 23 consists of registers 24,25, a decoder 26, memory devices 30,31,32,33 and 34, the address bus 12 is connected to the register 25 and the data bus 13 is connected to the register 24.
摘要翻译：目的：为了提供许多存储器件，通过使用具有一定行号的地址和数据总线，将一部分数据位转换为地址位。构成：微处理器11连接到存储器包23和具有地址总线12和数据总线13的显示装置19.存储器包23由寄存器24,25，解码器26，存储器件30,31,32，如图33和图34所示，地址总线12连接到寄存器25，数据总线13连接到寄存器24。

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