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    • 5. 发明专利
    • SIGNAL COLLISION DETECTION SYSTEM
    • JPS6284637A
    • 1987-04-18
    • JP22536785
    • 1985-10-09
    • YAGI ANTENNAHITACHI LTD
    • MORIFUJI MOTOYOSHINISHIZAWA TAKAHIKOTERADA MATSUAKIYAGYU KAZUO
    • H04L12/40
    • PURPOSE:To detect a signal collision at low cost with high precision by detecting whether there is a down high frequency signal received from the computer of another station through a coaxial cable for the 1st time when data from each computer is transmitted, and transmitting the data with an up high frequency signal unless there is the high frequency signal of another station on the coaxial cable. CONSTITUTION:A pulse signal is normally inputted to a processing part as effective data when the pulse signal is communication data of another computer or this computer and the waveform 103 of a carrier detecting circuit 56 is '1', but if a collision occurs, a pulse Y7 is outputted to a line 422 to make the data ineffective and the transmission is interrupted immediately when the data is transmitted. Then, when there is no down high frequency signal, namely, when the output of the carrier detecting circuit 56 is '0', the unmodulated up high frequency signal is transmitted again to confirm that the collision does not occur, and the data is sent out to make a communication with another computer.
    • 6. 发明专利
    • DEMODULATION CIRCUIT
    • JPH01114241A
    • 1989-05-02
    • JP27213287
    • 1987-10-28
    • YAGI ANTENNAHITACHI LTD
    • MORIFUJI MOTOYOSHIKOYAMA KATSUTOFUKUZAWA JUNJITERADA MATSUAKI
    • H04L27/156H04L27/14
    • PURPOSE:To demodulate a particular modulated wave where the combination form of switching time is changed, as well within the time of one bit by directly holding the output pulse of a reception circuit by a first shift register, and at the same time, inverting it, and holding it by a second shift register, and detecting it by a matrix circuit. CONSTITUTION:The output pulse of the reception circuit 22 is held directly by the first shift register 23, and at the same time, is inverted, and is held by the second shift register 27 as well, and '0', '1' of the data signal outputted by these shift registers 23, 27 is detected by the matrix circuit 28, and is demodulated through a gate circuit 29 and a latch circuit 30 into '0', '1' or a particular data signal corresponding to the output pulse of the reception circuit varying variously within one bit period of the data signal. Thus, by including this particular data in the transmission format of the data signal, the necessary data and a delimiter or a preamble indicating the start or the finish of the data can be easily distinguished, and the reliability of the contents of the data at the time of data transmission is improved.