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    • 2. 发明专利
    • ORTHOGONAL FREQUENCY DIVISION MULTIPLEX SIGNAL TRANSMITTING SYSTEM, TRANSMITTER AND RECEIVER
    • JP2001119364A
    • 2001-04-27
    • JP2000290216
    • 2000-09-25
    • VICTOR COMPANY OF JAPAN
    • KANEKO KEIICHI
    • H04J11/00
    • PROBLEM TO BE SOLVED: To solve the problems that there is a fixed limit in much more accuracy improvement since the amplitude characteristic difference or phase characteristic difference of I signal and Q signal becomes the direct cause of code error and that a characteristic change can not be corrected while a reference signal is not transmitted. SOLUTION: On the transmitting side, the known reference signal is transmitted by a specified carrier wave among plural carrier waves composing an OFDM signal, the carrier wave for transmitting the known reference signal is designated by a symbol number to be transmitted by a prescribed carrier wave, and the reference signal is transmitted while being successively and cyclically changed at the interval of a fixed period. On the receiving side, the reference signal is demodulated by a demodulation circuit 311 and transmission line characteristics are detected by a detecting circuit 312. A first correction expression is calculated from the detected transmission line characteristics and stored by a first correction expression deriving and holding circuit 313. The signal is decoded by a first correcting circuit 314 while using this correction expression. Further, the output signal of this correcting circuit 314 is corrected by newly calculating a second correction expression so that high-speed change characteristics can be corrected.
    • 5. 发明专利
    • ORTHOGONAL FREQUENCY-DIVISION MULTIPLE SIGNAL TRANSMISSION METHOD AND RECEIVER USED THEREFOR
    • JPH10135924A
    • 1998-05-22
    • JP28835596
    • 1996-10-30
    • VICTOR COMPANY OF JAPAN
    • KANEKO KEIICHI
    • H04L27/38H04J11/00H04L27/22
    • PROBLEM TO BE SOLVED: To provide an orthogonal frequency-division multiple signal transmission method by which out of symbol synchronization is minimized and the error caused by coefficient averaging between adjacent carriers is reduced, and to provide a receiver used therefor. SOLUTION: An N point discrete Fourier transmission(DFT) multi-value quadrature amplitude modulation(QAM) decoding circuit 31 decodes a symbol number and a reference signal, detects a transmission line characteristic from the reference signal, calculates a correction equation from the transmission line characteristic and stores it, obtains an integration value of an approximated value for each prescribed period by using the coefficient of the transmission line characteristic, so as to calculate an approximated value of a phase difference between a couple of carriers in a vicinity among a plurality of carriers as to each of carriers of the set number, the integration value this input is compared with the value at a preceding input and a forward signal or a backward signal is outputted, depending on the comparison result. A guard interval period processing circuit 30 adjusts it so that an integrated value of a DFT window, based on the symbol synchronization signal is adjusted based on the forward signal or the backward signal.
    • 9. 发明专利
    • DISK DRIVING DEVICE
    • JPS626407A
    • 1987-01-13
    • JP14297685
    • 1985-06-29
    • VICTOR COMPANY OF JAPAN
    • KANEKO KEIICHIMIYAZAKI TAKESHI
    • G11B5/09
    • PURPOSE:To improve the efficiency of a format by providing a delay means for delaying an erase gate signal for turning on/off a tonnel erase head from a write gate signal for turning on/off a recording/reproducing head by a time corresponding to respective detected outputs of a detecting means. CONSTITUTION:Respective delay lines 41-4n delay a write gate signal S2 by respective inherent delay times and output erase gate signals S1. The signals S1 are supplied to an AND gate circuit 15 to control the gate of the circuit 15. On the other hand, erase current is supplied from an erasing circuit 16 to the circuit 15 and the erase current is supplied to an E head 2 only for a period that the gate is opened to executed tonnel erasing. Thereby, the erase gate signals S1 obtained by delaying the write gate signal S2 only by the delay time in each cylinder are obtained. Consequently, the efficiency of the format is improved.