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1. 发明专利

JP2008010608A Wet etching method, damaged layer removing method, semiconductor device manufacturing method, and semiconductor substrate manufacturing method 有权
标题翻译：湿蚀刻方法，破损层去除方法，半导体器件制造方法和半导体衬底制造方法
公开(公告)号：JP2008010608A
公开(公告)日：2008-01-17
申请号：JP2006178976
申请日：2006-06-29
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KIGAMI MASAHITO , HAYASHI EIKO , SUGIMOTO MASAHIRO
IPC分类号： H01L21/308 , H01L33/32 , H01L33/44 , H01S5/323
摘要： PROBLEM TO BE SOLVED: To provide a wet etching method of a group III nitride semiconductor, a damaged layer removing method, a semiconductor device manufacturing method, and a semiconductor substrate manufacturing method. SOLUTION: On a GaN substrate 10 whose front surface is an R plane, an interlayer insulation film 11 formed of SiO 2 is formed (Figure 1A). Then, the interlayer insulation film 11 is dry-etched (Figure 1B) to form a contact hole 12. During this process, a damaged layer 13 is formed. Thereafter, using a TMAH aqueous solution having a concentration of 25% and a temperature of 90°C, wet etching is conducted. Since the damaged layer 13 is an R plane, it is etched and removed (Figure 1C) during the wet etching. Then, a metal film 14 is formed (Figure 1D). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供III族氮化物半导体的湿蚀刻方法，损伤层去除方法，半导体器件制造方法和半导体衬底制造方法。解决方案：在其表面为R平面的GaN衬底10上形成由SiO 2 形成的层间绝缘膜11（图1A）。然后，将层间绝缘膜11干蚀刻（图1B）以形成接触孔12.在此过程中，形成损伤层13。此后，使用浓度为25％，温度为90℃的TMAH水溶液，进行湿法蚀刻。由于损伤层13是R平面，因此在湿蚀刻期间蚀刻和去除（图1C）。然后，形成金属膜14（图1D）。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007227621A Semiconductor device with insulated-gate structure and its manufacturing method 审中-公开
标题翻译：具有绝缘门结构的半导体器件及其制造方法
公开(公告)号：JP2007227621A
公开(公告)日：2007-09-06
申请号：JP2006046641
申请日：2006-02-23
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SOEJIMA SHIGEMASA , UESUGI TSUTOMU , KIGAMI MASAHITO , HAYASHI EIKO , UEDA HIROYUKI , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide an insulated-gate structure having a high reliability in a semiconductor device using a nitride semiconductor. SOLUTION: The insulated-gate structure 10 has a semiconductor region 12 consisting of gallium nitride introducing magnesium as impurities. The insulated-gate structure 10 is brought into contact with the semiconductor region 12, and has a first insulating film 14 consisting of aluminum nitride substantially introducing no impurity. The insulated-gate structure 10 has a second insulating film 16 consisting of silicon oxide isolated from the semiconductor region 12 by the first insulating film 14. The insulated-gate structure 10 further has a gate electrode 18 opposed to the semiconductor region 12 through the first insulating film 14. A nitride semiconductor shown in general formula Al x Ga y In 1-x-y N (where 0≤x≤1, 0≤y≤1 and 0≤1-x-y≤1) is used for the semiconductor region 12. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在使用氮化物半导体的半导体器件中具有高可靠性的绝缘栅结构。解决方案：绝缘栅结构10具有由作为杂质的镁引入的氮化镓组成的半导体区域12。绝缘栅结构10与半导体区域12接触，并且具有由氮化铝组成的基本不引入杂质的第一绝缘膜14。绝缘栅结构10具有由半导体区域12通过第一绝缘膜14隔离的由氧化硅构成的第二绝缘膜16.绝缘栅结构10还具有通过第一绝缘栅极结构10与半导体区域12相对的栅极电极18 绝缘膜14.通式Al所示的氮化物半导体在 1-xy N（其中0≤x≤1,0 ≤y≤1且0≤1-xy≤1）用于半导体区域12.版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007173742A Manufacturing method of nitride semiconductor device 有权
标题翻译：氮化物半导体器件的制造方法
公开(公告)号：JP2007173742A
公开(公告)日：2007-07-05
申请号：JP2005372956
申请日：2005-12-26
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , UEDA HIROYUKI , HAYASHI EIKO , SOEJIMA SHIGEMASA , KANECHIKA MASAKAZU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To suppress a phenomenon in which the conductivity of a p-type nitride semiconductor is inserted in a process for exposing one portion of the surface of a p-type nitride semiconductor, by containing an n-type impurity or etching an i-type nitride semiconductor partially while being formed on the surface of a p-type nitride semiconductor region. SOLUTION: An intermediate layer is formed at a prescribed region on the surface of the p-type nitride semiconductor region, and then an n-type or i-type semiconductor region is formed. A prescribed region of the n-type or i-type semiconductor region is machined so that it reaches the intermediate layer, and only the intermediate layer is etched selectively for removal. Etchant for removing the intermediate layer can expose the surface without inverting the conductivity type of the surface of the p-type nitride semiconductor, by selecting a material without modifying a nitride semiconductor. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制在用于暴露p型氮化物半导体的一部分表面的工艺中插入p型氮化物半导体的导电性的现象，通过含有n型杂质或者在形成在p型氮化物半导体区域的表面上的同时蚀刻i型氮化物半导体。解决方案：在p型氮化物半导体区域的表面上的规定区域形成中间层，然后形成n型或i型半导体区域。加工n型或i型半导体区域的规定区域使其到达中间层，并且只有中间层被选择性地蚀刻去除。用于去除中间层的蚀刻剂可以通过选择不修饰氮化物半导体的材料来暴露表面而不颠倒p型氮化物半导体的表面的导电类型。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005050913A Semiconductor device having current sensing function 有权
标题翻译：具有电流感应功能的半导体器件
公开(公告)号：JP2005050913A
公开(公告)日：2005-02-24
申请号：JP2003203878
申请日：2003-07-30
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： NISHIBE YUJI , UESUGI TSUTOMU , KIGAMI MASAHITO , HAYASHI EIKO , OTA NORIKAZU , HAMADA KIMIMORI , TAKATANI HIDESHI , TOSHIMA HIDEKI
IPC分类号： H01L29/78 , H01L27/04 , H01L29/06
CPC分类号： H01L29/7815 , H01L29/0696 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To suppress the fluctuation of the current sensing ratio of a semiconductor device at an atmospheric temperature. SOLUTION: A semiconductor device forms a main region 1 in which main current flows and a sensing region 2 in which branched current flows on the same substrate, and numbers of cells in the sense cell region 2 amount to not more than 0.1% of the numbers in the main cell region. At that time, a resistant temperature coefficient of a peripheral cell existing along the boundary of the regions is equal to that of an inside cell existing away from the boundary. Otherwise, the ratio of the numbers of the peripheral cell and the inside cell is equal in the main region 1 and the sensing region 2. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：抑制半导体器件在大气温度下的电流感测比的波动。解决方案：半导体器件形成主电流流过的主区域1和在同一衬底上流动分支电流的感测区域2，感测单元区域2中的单元数量不大于0.1％的主单元格区域中的数字。此时，沿着该区域的边界存在的周边电池的电阻温度系数与远离边界的内部电池的电阻温度系数相等。否则，主区域1和感测区域2中的外围单元和内部单元的数量的比率相等。（C）2005，JPO和NCIPI

5. 发明专利

JP2007266203A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007266203A
公开(公告)日：2007-10-11
申请号：JP2006087683
申请日：2006-03-28
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , KANECHIKA MASAKAZU , KIGAMI MASAHITO , HAYASHI EIKO , UEDA HIROYUKI , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/06 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/80 , H01L29/808 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To achieve a semiconductor device that is superior in on-characteristics and the breakdown voltage.
SOLUTION: A protective film 3 consisting of Al
2 O
3 crystal whose thickness being about 0.1 μm-0.3 μm is laminated on the top face of semiconductor layers 1 and 2. It is sufficient that this film thickness be the thickness for it to function as a diffusion barrier for impurity or implantation barrier for a carrier. This protective film 3 can be formed by the crystal growing of the Al
2 O
3 crystal, and the crystal growing of a thick GaN crystal layer can be carried out widely and easily further thereon. A thick high-breakdown-voltage insulating film 4, formed over a wide area is a semiconductor crystal layer laminated by such a crystal growth, and is formed of an intrinsic GaN crystal whose film thickness is about 20 μm. A protective film 5, consisting of Al
2 O
3 crystal, is formed by about 0.1 μm, further, thereon. This protective film 5 functions as the implantation barrier layer for the carrier or the protective film for preventing the diffusion (infiltration) of the impurity into the high-withstand-voltage insulating film 4.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：实现导通特性和击穿电压优异的半导体器件。
解决方案：由半导体层1的顶面上层叠由厚度为约0.1μm〜0.3μm的AlS / SiO 3结构构成的保护膜3，该膜厚度为其用作载体的杂质扩散阻挡层或植入阻挡层的厚度就足够了。该保护膜3可以通过Al 2 SB 3 O 3 / SiO 3晶体的晶体生长而形成，并且可以广泛且容易地进行厚GaN晶体层的晶体生长进一步在其上。在宽范围内形成的厚的高耐压绝缘膜4是通过这种晶体生长层叠的半导体晶体层，并且由膜厚度为约20μm的本征GaN晶体形成。由Al 2 SB 3结晶组成的保护膜5在其上进一步形成约0.1μm。该保护膜5用作用于防止杂质向高耐压绝缘膜4的扩散（渗入）的载体或保护膜的注入阻挡层。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007258578A Group iii nitride compound semiconductor, method for making p-type semiconductor therefrom, insulation separation method, and transistor using the same 审中-公开
标题翻译： III族氮化物化合物半导体，其制造P型半导体的方法，绝缘分离方法和使用其的晶体管
公开(公告)号：JP2007258578A
公开(公告)日：2007-10-04
申请号：JP2006083574
申请日：2006-03-24
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KIGAMI MASAHITO , HAYASHI EIKO , SUGIMOTO MASAHIRO
IPC分类号： H01L21/265 , H01L21/336 , H01L21/338 , H01L21/761 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a method for making a p-type semiconductor out of a group III nitride compound semiconductor and an element having the p-type region. SOLUTION: Magnesium (Mg) is partially injected into a group III nitride compound semiconductor on a plane surface, and thereafter, the magnesium is thermally diffused in a horizontal direction on the plane surface and in a direction vertical to the plane surface, thus making the diffused region a p-type region. Then, silicon (Si) is added to the injected area to form an n-type region. This can exclude an injected area of high resistance. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供从III族氮化物半导体和具有p型区域的元件制造p型半导体的方法。解决方案：将镁（Mg）部分地注入到平面上的III族氮化物化合物半导体中，之后，镁在平面上和垂直于平面的方向上在水平方向上热扩散，从而使扩散区域成为p型区域。然后，将硅（Si）加入到注入区域中以形成n型区域。这可以排除高电阻的注入区域。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006253224A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006253224A
公开(公告)日：2006-09-21
申请号：JP2005064397
申请日：2005-03-08
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KIGAMI MASAHITO , HAYASHI EIKO , SUGIMOTO MASAHIRO
IPC分类号： H01L29/786 , H01L21/22 , H01L21/324 , H01L21/338 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To reduce the threshold voltage of an MIS type gate structure in a semiconductor device using a gallium nitride (GaN).
SOLUTION: The semiconductor device 10 includes the semiconductor layer 32 of the gallium nitride (GaN) containing a magnesium, and a gate electrode 58 which is arranged opposite to the semiconductor layer 32 through a gate insulating film 52. A local region 34 is formed in which hydrogen atom is locally unevenly distributed in a region opposite to the gate electrode 58 of the semiconductor layers 32. The magnesium is inactivated in the local region 34.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了降低使用氮化镓（GaN）的半导体器件中的MIS型栅极结构的阈值电压。解决方案：半导体器件10包括含有镁的氮化镓（GaN）的半导体层32和通过栅极绝缘膜52与半导体层32相对配置的栅电极58.局部区域34 形成其中氢原子局部不均匀地分布在与半导体层32的栅电极58相对的区域中。镁在局部区域34中失活。（C）2006，JPO和NCIPI

8. 发明专利

JP2008021756A Group iii nitride semiconductor device 审中-公开
标题翻译： III类氮化物半导体器件
公开(公告)号：JP2008021756A
公开(公告)日：2008-01-31
申请号：JP2006191100
申请日：2006-07-12
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , KACHI TORU , UESUGI TSUTOMU , UEDA HIROYUKI , KIGAMI MASAHITO , SOEJIMA SHIGEMASA , HAYASHI EIKO , KANECHIKA MASAKAZU
IPC分类号： H01L29/12 , H01L21/28 , H01L21/338 , H01L29/417 , H01L29/778 , H01L29/78 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To crystal-grow an n- or i-type group III nitride semiconductor on the surface of a p-type group III nitride semiconductor, and to expose the surface of the p-type group III nitride semiconductor without etching a part of the n- or i-type group III nitride semiconductor.
SOLUTION: An impurity diffusion preventing film 36 is provided on a part of the surface of a first group III nitride semiconductor region 28 containing a p-type impurity. An n-type impurity-containing or i-type second group III nitride semiconductor region 44 is provided on a position where it is opposite to the first group III nitride semiconductor region 28 with the interposition of the preventing film 36. Also, a p-type impurity-containing third group III nitride semiconductor region 30 is provided on a position where it is opposite to the first group III nitride semiconductor region 28 without the interposition of the preventing film 36.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在p型III族氮化物半导体的表面上晶体生长n型或i型III族氮化物半导体，并露出p型III族氮化物半导体的表面而不蚀刻n型或i型III族氮化物半导体的一部分。解决方案：在包含p型杂质的第一III族氮化物半导体区域28的表面的一部分上设置杂质扩散防止膜36。通过插入防止膜36，在与第一III族氮化物半导体区域28相反的位置处设置n型杂质或i型第二III族氮化物半导体区域44。含有杂质的第三III族氮化物半导体区域30设置在与第一III族氮化物半导体区域28相对的位置，而不插入防止膜36.版权所有：（C）2008，JPO＆INPIT

9. 发明专利

JP2007324549A Dislocation detecting method for semiconductor crystal 审中-公开
标题翻译：半导体晶体的离散检测方法
公开(公告)号：JP2007324549A
公开(公告)日：2007-12-13
申请号：JP2006156643
申请日：2006-06-05
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KIGAMI MASAHITO , HAYASHI EIKO , SUGIMOTO MASAHIRO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To easily and safely detect dislocation of GaN in a method of easily detecting a defect owing to dislocation of group III nitride semiconductor crystal for which Ga is essential.
SOLUTION: Crystal of GaN is etched for one hour with a TMAH (tetramethyl ammonium hydroxide) of 25% in concentration warmed at 85°C. Then an etch pitch is formed on a crystal surface of GaN. The etch pit is formed at a dislocation part, so the dislocation can be detected through the etch pit. Further, the dislocation density can be measured by counting etch pits through an optical microscope etc., and then the quality of the crystal can be evaluated.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了容易地检测由于Ga所必需的III族氮化物半导体晶体的位错导致的缺陷的容易检测的方法，容易且安全地检测GaN的位错。解决方案：在85℃下加热的浓度为25％的TMAH（四甲基氢氧化铵）蚀刻GaN的晶体1小时。然后在GaN的晶体表面上形成蚀刻间距。蚀刻坑形成在位错部分，因此可以通过蚀刻坑检测位错。此外，位错密度可以通过光刻显微镜等对蚀刻坑进行计数来测量，然后可以评估晶体的质量。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2006114802A Structure with upper layer laminated on group iii-v semiconductor layer and its manufacturing method 有权
标题翻译：上层层叠在III-V族半导体层上的结构及其制造方法
公开(公告)号：JP2006114802A
公开(公告)日：2006-04-27
申请号：JP2004302514
申请日：2004-10-18
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KIGAMI MASAHITO , HAYASHI EIKO , SOEJIMA SHIGEMASA , SUGIMOTO MASAHIRO
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method capable of removing a gallium oxide film formed on the surface as a natural oxide film without damaging the surface of a GaN layer 24 in manufacturing a structure with the upper layer laminated on the surface of the GaN layer 24.
SOLUTION: This method manufactures a structure where an SiO
2 layer 26 made of oxide silicon is laminated on the surface of a GaN layer 24. It comprises a process for exposing the surface of the GaN layer 24 to gas including non-plasma ammonia, and a process for laminating the SiO
2 layer 26 on the surface of the GaN layer 24 exposed to the ammonia gas.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够除去形成在表面上的氧化镓膜作为天然氧化物膜的方法，而不会在制造具有层叠在表面上的上层的结构的GaN层24的表面上 GaN层24.解决方案：该方法制造其中由氧化硅制成的SiO 2 SB 2层26层压在GaN层24的表面上的结构。它包括一种将包括非等离子体氨的气体的GaN层24的表面，以及暴露于氨气的GaN层24的表面上层叠SiO 2 SB 2层26的工序。版权所有（C）2006，JPO＆NCIPI

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