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1. 发明专利

JP2009099165A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009099165A
公开(公告)日：2009-05-07
申请号：JP2007267132
申请日：2007-10-12
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SUZUKI AZUMA , OTSUKA NOBUAKI , YABE TOMOAKI , HIRABAYASHI OSAMU , TOHATA AKISHI
IPC分类号： G11C29/04 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To easily increase the number of redundancies in an SRAM, etc., by reducing area penalty in a similar way as a conventional dynamic column shift method.
SOLUTION: This semiconductor storage device includes a column shift redundancy circuit for dynamically shifting columns when an address input hits on a defective address. The redundancy column cell is divided into N pieces and column addresses different from each other are allocated to the divided cells.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过以与常规动态列移位法相似的方式减少面积损失，可以容易地增加SRAM等中的冗余数量。解决方案：该半导体存储装置包括列移位冗余电路，用于当地址输入命中在缺陷地址时动态地移位列。将冗余列单元划分为N个，并将彼此不同的列地址分配给分割单元。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009048671A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009048671A
公开(公告)日：2009-03-05
申请号：JP2007210885
申请日：2007-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G11C11/412
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves both write characteristics and tolerance against disturb caused by variations of threshold voltage or the like and reduction of voltage, and suppresses increase in area, increase in power and deterioration of speed property. SOLUTION: The semiconductor storage device is provided with: a memory cell containing a first inverter IV1 to which an input end and output end are connected to cross respectively and a second inverter IV2; a reference supply wiring VSSCL which supplies reference voltage VSSC to the first inverter IV1; a reference supply wiring VSSCR which supplies reference voltage VSSC to the second inverter IV2; bit lines BL and /BL connected to the memory cell; and transfer gates TL1 and TL2 and transfer gates TR1 and TR2 which control impedance in the reference supply wirings VSSCL and VSSCR according to voltages of bit lines BL and /BL respectively. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储装置，其提高写入特性和由阈值电压等的变化引起的干扰和电压的降低，并且抑制面积的增加，功率的增加和速度的劣化属性。解决方案：半导体存储装置设置有：存储单元，其包含第一反相器IV1，输入端和输出端分别连接到第一反相器IV1和第二反相器IV2; 将参考电压VSSC提供给第一反相器IV1的参考电源线VSSCL; 向第二反相器IV2供给基准电压VSSC的基准电源配线VSSCR; 连接到存储单元的位线BL和/ BL; 以及分别根据位线BL和/ BL的电压来控制参考电源配线VSSCL和VSSCR中的阻抗的传输门TL1和TL2以及传输门TR1和TR2。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008146734A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2008146734A
公开(公告)日：2008-06-26
申请号：JP2006331992
申请日：2006-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKANO TAKESHI , YABE TOMOAKI , OTSUKA NOBUAKI
IPC分类号： G11C11/41
CPC分类号： G11C7/18
摘要： PROBLEM TO BE SOLVED: To increase the operation speed of a semiconductor memory.
SOLUTION: This semiconductor memory has sub-arrays connecting the memory cells arranged in matrixes, local bit lines connected to memory cells arranged in the column direction in the sub-arrays, global bit lines connected to the local bit lines, and a column decoder connected to the global bit lines. However, in the farthest sub-array formed in an area most apart from the column decoder among those sub-arrays, the global bit lines are not formed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高半导体存储器的操作速度。解决方案：该半导体存储器具有连接以矩阵排列的存储单元的子阵列，连接到子阵列中的列方向上布置的存储单元的本地位线，连接到局部位线的全局位线，以及列解码器连接到全局位线。然而，在这些子阵列中与列解码器最远的区域中形成的最远的子阵列中，不形成全局位线。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2010187122A Level shifter circuit 有权
标题翻译：水平更换电路
公开(公告)号：JP2010187122A
公开(公告)日：2010-08-26
申请号：JP2009028902
申请日：2009-02-10
申请人： Toshiba Corp , 株式会社東芝
发明人： UCHINO YUKINORI , OTSUKA NOBUAKI
IPC分类号： H03K19/0185
CPC分类号： H03K3/356113 , H03K3/012
摘要： PROBLEM TO BE SOLVED: To provide a level shifter circuit which is flexibly made correspondent to transition to low voltage driving of an LSI and enables high operation speed. SOLUTION: A power source VDD1 for internal circuits and a power source VDD2 for interface to external circuits have a relation of VDD1 COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种灵活地对应于向LSI的低电压驱动转变的电平移位电路，并且能够实现高运行速度。
解决方案：内部电路的电源VDD1和与外部电路接口的电源VDD2的关系为VDD1

5. 发明专利

JP2009048670A Semiconductor circuit 审中-公开
标题翻译：半导体电路
公开(公告)号：JP2009048670A
公开(公告)日：2009-03-05
申请号：JP2007210884
申请日：2007-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： IMAI KIMIMASA , OTSUKA NOBUAKI , KUSHIDA KEIICHI
IPC分类号： G11C11/417
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor circuit capable of preventing current leakage which occurs during standing-by and suppressing an increase in power consumption even if second power is higher than first power when a signal output from a circuit using the first power is entered to a circuit using the second power.
SOLUTION: The semiconductor circuit is provided with a first power source circuit using first power VDD1 supplied from the outside, a second power source circuit using second power VDD2 supplied from the outside, and first and second inverters IV1 and IV2 connected between the first and second power source circuits to convert an output signal from the first power source circuit into an input signal to the second power source circuit. When the second power VDD2 is higher than the first power VDD1, during standing-by, the output signal from the first power source circuit is at a low level, and entered to the first inverter IV1.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止在待机期间发生的电流泄漏的半导体电路，并且即使当从使用第一个电路的电路输出的信号的第二功率高于第一功率时，即使第二功率高于第一功率，也抑制了功率消耗的增加使用第二个电源将电源输入电路。解决方案：半导体电路使用从外部提供的第一电源VDD1的第一电源电路，使用从外部提供的第二电源VDD2的第二电源电路和连接在第二电源VDD1之间的第一和第二反相器IV1和IV2 第一和第二电源电路，用于将来自第一电源电路的输出信号转换成输入信号到第二电源电路。当第二电源VDD2高于第一电源VDD1时，在待机期间，来自第一电源电路的输出信号处于低电平，并输入到第一反相器IV1。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008177360A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2008177360A
公开(公告)日：2008-07-31
申请号：JP2007009397
申请日：2007-01-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIDA KEIICHI , OTSUKA NOBUAKI
IPC分类号： H01L21/8244 , G11C11/41 , H01L27/11
CPC分类号： G11C7/08 , G11C5/02 , G11C7/227 , G11C8/12 , G11C11/412 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory using a hierarchical bit line system for reducing an area. SOLUTION: The semiconductor memory includes: a plurality of local bit lines LBL for selecting a row of each memory cell array 11; a plurality of local sense amplifiers 12, each of which is arranged in each of two memory cell arrays 11 and detects data to be transferred from the memory cell via each local bit line LBL; a plurality of replica cell groups 15 arranged in response to the plurality of local sense amplifiers 12; a plurality of replica bit lines RBL respectively connected to the plurality of replica cell groups 15; a plurality of active circuits 14 for activating the local sense amplifiers 12, based on the potential of the replica bit lines RBL; and a contact region 17 where contacts for supplying power to the well region of a transistor constituting memory cells are arranged. The two memory cell arrays 11 connected to the different local sense amplifiers 12 are adjacently arranged without holding the contact region 17 between them. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用分层位线系统来减少面积的半导体存储器。解决方案：半导体存储器包括：用于选择每个存储单元阵列11的行的多个局部位线LBL; 多个本地读出放大器12，每个本地读出放大器12布置在两个存储单元阵列11的每一个中，并且经由每个局部位线LBL检测要从存储单元传送的数据; 多个复制单元组15，其响应多个本地读出放大器12布置; 分别连接到多个复制单元组15的多个复制位线RBL; 多个用于激活本地读出放大器12的有源电路14，基于复制位线RBL的电位; 以及接触区域17，其中布置有用于向构成存储单元的晶体管的阱区域供电的触点。连接到不同的局部感测放大器12的两个存储单元阵列11相邻布置，而不在它们之间保持接触区域17。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008065863A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008065863A
公开(公告)日：2008-03-21
申请号：JP2006239385
申请日：2006-09-04
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKEYAMA YASUHISA , OTSUKA NOBUAKI
IPC分类号： G11C11/412 , G11C11/41
摘要： PROBLEM TO BE SOLVED: To improve data holding stability in a memory cell.
SOLUTION: This semiconductor memory device includes inverter circuits IC1 and IV2 constituted of MOS transistors; a storage node N1 connected to the output terminal of the inverter circuit IV1 and the input terminal of the inverter circuit IV2; a storage node N0 connected to the input terminal of the inverter circuit IV1 and the output terminal of the inverter circuit IV2; a first writing path with which the storage node N1 and a bit line BL0 are connected during data writing and which is controlled by a column selection signal; a writing path with which the storage node N0 are a bit line BL1 are connected during data writing and which is controlled by the column selecting signal; and a reading path through which data stored in the storage node N1 or N0 are transferred to the bit line BL0 during data writing.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高存储单元中的数据保持稳定性。解决方案：该半导体存储器件包括由MOS晶体管构成的反相器电路IC1和IV2; 连接到逆变器电路IV1的输出端子和反相器电路IV2的输入端子的存储节点N1; 连接到逆变器电路IV1的输入端子和反相器电路IV2的输出端子的存储节点N0; 存储节点N1和位线BL0在数据写入期间连接并由列选择信号控制的第一写入路径; 在数据写入期间，存储节点N0是位线BL1的写入路径被连接，并且由列选择信号控制; 以及在数据写入期间将存储在存储节点N1或N0中的数据传送到位线BL0的读取路径。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007250586A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2007250586A
公开(公告)日：2007-09-27
申请号：JP2006067988
申请日：2006-03-13
申请人： Toshiba Corp , 株式会社東芝
发明人： OTSUKA NOBUAKI , HIRABAYASHI OSAMU
IPC分类号： H01L21/8244 , G11C11/413 , H01L27/10 , H01L27/11
CPC分类号： G11C11/417 , G11C5/148
摘要： PROBLEM TO BE SOLVED: To suppress noise while reducing the area in a semiconductor memory where cell bias is controlled under sleep state. SOLUTION: The semiconductor device comprises a memory cell array 11 of a plurality of memory cells arranged in a cell array region, a source potential line for supplying source potential to the memory cell, a switch element group 21 arranged contiguously to the memory cell array 11 in the cell array region and making the source potential line and the ground potential electrically noncontact under sleep state of the memory cell, a p-type first MIS transistor 23 connected between the source potential line and the ground potential and clamping the source potential under sleep state, and a bias formation circuit 22 arranged in the peripheral circuit region on the outside of the cell array region and supplying a bias potential to the gate terminal of the first MIS transistor 23. The first MIS transistor is arranged in the peripheral circuit region. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：抑制噪声，同时减少在睡眠状态下控制电池偏压的半导体存储器中的面积。解决方案：半导体器件包括布置在单元阵列区域中的多个存储单元的存储单元阵列11，用于向存储单元提供源极电位的源极电位线，与存储器相邻布置的开关元件组21 单元阵列11，并且使源极电位线和接地电位在存储单元的睡眠状态下电接触不连续; p型第一MIS晶体管23连接在源极电位线与接地电位之间并夹持源极以及设置在电池阵列区域外侧的外围电路区域中的偏置形成电路22，并向第一MIS晶体管23的栅极端提供偏置电位。第一MIS晶体管配置在周边电路区域。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006313643A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2006313643A
公开(公告)日：2006-11-16
申请号：JP2006227958
申请日：2006-08-24
申请人： Toshiba Corp , 株式会社東芝
发明人： TANZAWA TORU , ATSUMI SHIGERU , BANBA HIRONORI , YAMADA SEIJI , MORI SEIICHI , KURIYAMA MASAO , OTSUKA NOBUAKI
IPC分类号： G11C16/02 , G11C29/34
摘要： PROBLEM TO BE SOLVED: To ease constraint of number of bits which can be written simultaneously, for example, a data write and test period can be shortened, and to suppress test cost. SOLUTION: The memory is provided with; a memory core section comprising a plurality of cell array blocks equipped with a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines; and a means to write data simultaneously in a plurality of memory cells in one cell array block at the time of 1st data writing and write data simultaneously in a plurality of memory cells in a plurality of cell array blocks at the time of 2nd data writing. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了简化可以同时写入的位数的限制，例如，可以缩短数据写入和测试周期，并且抑制测试成本。
解决方案：提供内存; 存储器核心部分，包括配备有多个非易失性存储器单元，多个字线和多个位线的多个单元阵列块; 以及在第二数据写入时在第一数据写入时在一个单元阵列块中的多个存储单元中同时写入数据并在多个单元阵列块中的多个存储单元中同时写入数据的装置。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2005244101A Semiconductor device and its programming method 有权
标题翻译：半导体器件及其编程方法
公开(公告)号：JP2005244101A
公开(公告)日：2005-09-08
申请号：JP2004054910
申请日：2004-02-27
申请人： Toshiba Corp , 株式会社東芝
发明人： OTSUKA NOBUAKI , FUJII HIDETAKE , SASAKI TAKAHIKO
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/10 , H01L27/108 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To shorten the programming time of a fuse element. SOLUTION: A fuse link FL is arranged between a first terminal N1 and a second terminal N2. The first terminal N1, the second terminal N2, and the fuse link FL have a polysilicon layer 13 and an overlying layer 14 containing a metal element, and at least a part of the fuse link FL is an amorphous silicon layer. COPYRIGHT: (C)2005,JPO&NCIPI

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