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1. 发明专利

JP2010123731A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2010123731A
公开(公告)日：2010-06-03
申请号：JP2008295570
申请日：2008-11-19
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI YOSHIHIRO , KAWAGUCHI YUSUKE
IPC分类号： H01L21/336 , H01L29/41 , H01L29/417 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of reducing the thickness of a substrate without causing a crack and warpage.
SOLUTION: A semiconductor element substrate 18 is formed by forming a source electrode 16 and a gate takeout electrode on an element A on an n+ semiconductor layer 10a where the element A is formed. A grid-like groove 25 is so formed as to separate the element from the surface of the semiconductor element substrate 18 where the source electrode 16 and the gate takeout electrode are not formed into the wanted depth of the n+ semiconductor layer 10a. Resin 35 is packed between the groove 25 and the element with the source electrode 16 and the gate takeout electrode formed. In a state that the resin 35 is packed, the rear surface of the n+ semiconductor layer 10a is polished to a wanted thickness. A drain electrode 20 is formed at a place corresponding to the element A of the polished n+ semiconductor layer 10a. The drain electrodes 20 are pasted to a dicing tape 36, and a place where the resin 35 is packed is diced.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供能够减小基板的厚度而不引起裂纹和翘曲的半导体器件的制造方法。解决方案：通过在形成元件A的n +半导体层10a上的元件A上形成源电极16和栅极取出电极来形成半导体元件基板18。格栅状的槽25形成为将源极电极16和栅极取出电极未形成为半导体元件基板18的表面的元件分离成n +半导体层10a的有用深度。树脂35被填充在槽25和元件之间，源极电极16和栅极取出电极形成。在树脂35被填充的状态下，n +半导体层10a的后表面被抛光到想要的厚度。在对应于抛光的n +半导体层10a的元件A的位置处形成漏电极20。将漏电极20粘贴到切割胶带36上，并且将包装树脂35的部位切割。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010027719A Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：JP2010027719A
公开(公告)日：2010-02-04
申请号：JP2008184822
申请日：2008-07-16
申请人： Toshiba Corp , 株式会社東芝
发明人： AKIYAMA MIWAKO , KAWAGUCHI YUSUKE , YAMAGUCHI YOSHIHIRO
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/41766
摘要： PROBLEM TO BE SOLVED: To provide a power semiconductor device low in ON resistance and high in avalanche resistance. SOLUTION: In the power semiconductor device 1, the impurity concentration profile in a vertical direction of a p-type base contact layer 15 has a two-stage structure. That is, on an A-A' line, the impurity concentration reaches the highest value on an upper surface of the p-type base contact layer 15 and exhibits a minimal value C min at a position P min other than upper and lower surfaces and a maximal value C max at a position P max lower than the position P min . COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供低导通电阻和高雪崩电阻的功率半导体器件。解决方案：在功率半导体器件1中，p型基极接触层15的垂直方向上的杂质浓度分布具有两级结构。也就是说，在AA'线上，杂质浓度在p型基底接触层15的上表面达到最高值，并且在位置P 处呈现最小值C min min 以外的位置P max 以下的最大值C max 。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2008108962A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008108962A
公开(公告)日：2008-05-08
申请号：JP2006291291
申请日：2006-10-26
申请人： Toshiba Corp , 株式会社東芝
发明人： AKIYAMA MIWAKO , NAKAGAWA AKIO , KAWAGUCHI YUSUKE , ONO SHOTARO , YAMAGUCHI YOSHIHIRO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： PROBLEM TO BE SOLVED: To maintain the good tradeoff property of on-resistance and breakdown voltage which are the advantage of MOS transistors of floating construction, at the same time, to improve also turn-on property and switching loss in the time of turn-on of an element.
SOLUTION: In an epitaxial layer 12, a p-type embedded layer 13 A of the bottom is embeddedly formed and further a p-type connection layer 13B which connects the p-type embedded layer 13 and a p-type base layer 14 is embeddedly formed. The impurity concentration of the p-type connection layer 13B is smaller than that of the p-type embedded layer 13A. The p-type base layer 14 is formed by epitaxial growth on the upper surface of the epitaxial layer 12. In a trench T1, a gate electrode 16 composed of polysilicon etc. is embedded through a gate insulating film 15. The depth Dd (p-type embedded layer depth) of the p-type embedded layer 13A from the bottom of the p-type base layer 14 is larger than the distance (protruding distance) Dgp between the bottom face of the gate electrode 16 and the base layer 14.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了保持作为浮动结构的MOS晶体管的优点的导通电阻和击穿电压的良好权衡特性，同时，在时间上改善开启特性和开关损耗元素的开启。解决方案：在外延层12中，底部的p型嵌入层13A被嵌入地形成，并且还有一个连接p型嵌入层13和p型基极层的p型连接层13B 14嵌入地形成。 p型连接层13B的杂质浓度比p型嵌入层13A的杂质浓度小。 p型基极层14通过外延生长在外延层12的上表面上形成。在沟槽T1中，由多晶硅等构成的栅电极16通过栅极绝缘膜15嵌入。深度Dd（p p型嵌入层13A的厚度比p型基底层14的底部的距离（突出距离）Dgp大，与栅极电极16的底面和底层14之间的距离（突出距离）Dgp大。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008066708A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008066708A
公开(公告)日：2008-03-21
申请号：JP2007165879
申请日：2007-06-25
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAGUCHI YUSUKE , YAMAGUCHI YOSHIHIRO , ONO SHOTARO , NAKAGAWA AKIO , AKIYAMA MIWAKO , NAKAYAMA KAZUYA , YAMAGUCHI SHOICHI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces the channel resistance of a MOSFET to reduce the on-resistance of an element.
SOLUTION: The semiconductor device includes a first conductive drain layer 11, an epitaxial layer 12 formed on the drain layer 11, and a second conductive base layer 13 formed on the surface of the epitaxial layer 12. A plurality of gate electrodes 15 are formed via gate insulating layers 14 so that the base layer 13 is located between the gate electrodes 15. The width x of the base layer 13 located between the gate electrodes 15 is designated to be 0.3 μm or smaller.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种降低MOSFET的沟道电阻以减小元件的导通电阻的半导体器件。解决方案：半导体器件包括第一导电漏极层11，形成在漏极层11上的外延层12和形成在外延层12的表面上的第二导电基极层13.多个栅电极15 通过栅极绝缘层14形成，使得基极层13位于栅电极15之间。位于栅电极15之间的基极层13的宽度x被指定为0.3μm以下。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006179664A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006179664A
公开(公告)日：2006-07-06
申请号：JP2004371056
申请日：2004-12-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , KAWAGUCHI YUSUKE , YAMAGUCHI YOSHIHIRO , MATSUKI HIROFUMI , ARAI KIYOTAKA
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696
摘要： PROBLEM TO BE SOLVED: To improve avalanche resistance after reducing ON resistance in a semiconductor device such as a power MOSFET with a trench gate structure.
SOLUTION: A power MOSFET 21 has an n-type drift layer 10 and a p-type base layer 11 laminated and formed thereon. A trench gate 17 is formed to get at the n-type drift layer 10 passing through the p-type base layer 11. An n
+ -type source region 18 and a p
+ -type region 19 are formed on the p-type base layer 11. They are adjacently disposed alternately along a longitudinal direction of the trench gate 17. The n
+ -type source region 18 and the p
+ -type region 19 are disposed to intersect with each other having an inclination to the longitudinal direction of the trench gate 17.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在具有沟槽栅极结构的诸如功率MOSFET的半导体器件中降低导通电阻之后提高雪崩阻力。解决方案：功率MOSFET21具有层叠并形成在其上的n型漂移层10和p型基极层11。形成沟槽栅极17以便在通过p型基极层11的n型漂移层10处获得.n + SP / SP型源极区域18和ap 型区域19形成在p型基极层11上。它们沿着沟槽栅极17的纵向相互交替布置.n + SP +型源区域18和p < SP> + 型区域19设置成相对于沟槽栅极17的纵向具有倾斜度相互交叉。（C）2006，JPO和NCIPI

6. 发明专利

JP2004193630A High withstand voltage semiconductor element 有权
公开(公告)号：JP2004193630A
公开(公告)日：2004-07-08
申请号：JP2004064661
申请日：2004-03-08
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHIRO TOMOKO , YASUHARA NORIO , NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , OMURA ICHIRO , FUNAKI HIDEYUKI
IPC分类号： H01L29/74 , H01L21/02 , H01L21/336 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/786 , H01L29/861
CPC分类号： H01L29/407
摘要： PROBLEM TO BE SOLVED: To provide a dielectric isolation structured high withstand voltage semiconductor element capable of obtaining a sufficient high withstand voltage characteristic by a thin active layer. SOLUTION: The semiconductor element is provided with a semiconductor substrate and the active layer having a thickness of 0.3 μm or less comprising a high resistance semiconductor which is formed on the semiconductor substrate via an insulator film. For the active layer, impurity concentration distribution in a lateral direction forms steps varying from 2 to 10 steps. COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2009224811A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009224811A
公开(公告)日：2009-10-01
申请号：JP2009160256
申请日：2009-07-06
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA KAZUTOSHI , YAMAGUCHI YOSHIHIRO , KAWAGUCHI YUSUKE , ONO SHOTARO , NAKAGAWA AKIO
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a sufficiently reliable vertical or lateral MOSFET structure semiconductor device improved in a trade-off relation between on-state resistance and feedback capacitance.
SOLUTION: The semiconductor device includes a first conductivity type semiconductor layer, a pair of second conductivity type base regions selectively formed on a surface of the semiconductor layer, a first conductivity type source region selectively formed on the base region of each of the pair of the base regions, a second conductivity type electric field relaxation region selectively formed between the pair of base regions on the surface of the semiconductor layer, a first conductivity type semiconductor region formed between the electric field relaxation region and the base region with an impurity concentration higher than that in the semiconductor layer, a pair of gate electrodes formed via a gate insulation film on the surface of the base region between the source regions and the electric field relaxation region, and a source electrode connected to the source region.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供在导通状态电阻和反馈电容之间的权衡关系中改进的足够可靠的垂直或横向MOSFET结构半导体器件。解决方案：半导体器件包括第一导电类型半导体层，选择性地形成在半导体层的表面上的一对第二导电型基极区域，选择性地形成在每个的基极区域上的第一导电型源极区域一对基极区域，选择性地形成在半导体层的表面上的一对基极区域之间的第二导电型电场弛豫区域，形成在电场弛豫区域和具有杂质的基极区域之间的第一导电型半导体区域浓度高于半导体层的浓度，在源极区域和电场弛豫区域之间的基极区域的表面上经由栅极绝缘膜形成的一对栅极电极和连接到源极区域的源极电极。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2007027327A Trench gate type semiconductor device and manufacturing method thereof 有权
标题翻译： TRENCH门式半导体器件及其制造方法
公开(公告)号：JP2007027327A
公开(公告)日：2007-02-01
申请号：JP2005206039
申请日：2005-07-14
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI YOSHIHIRO , KAWAGUCHI YUSUKE , ONO SHOTARO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide a trench gate type semiconductor device capable of reconciling the securement of avalanche resistance and the reduction in ON resistance, and to provide its manufacturing method.
SOLUTION: The semiconductor comprises a trench gate structure; an n-type source layer having an upper surface located at the opposite position to a gate electrode via a part of a gate insulating film; a p-type base layer located at the opposite position to a gate electrode adjacent to the n-type source layer and via a another part of the gate insulating film; an n-type semiconductor layer located at the opposite position to the gate electrode via one another part of the gate insulating film, which is adjacent to the p-type base layer without contacting with the n-type source layer; and a p-type contact layer wherein at least the two peaks are located at the shallower position than the formation depth from the upper surface of the n-type source layer, which is brought into contact with the n-type source layer and the p-type base layer and also has an upper surface which constitutes the same plane as the upper surface of this n-type source layer, while a profile of an impurities concentration value has at least two peaks viewed from this upper surface to the depth direction.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够调节雪崩电阻的固定和导通电阻的降低的沟槽栅型半导体器件，并提供其制造方法。解决方案：半导体包括沟槽栅极结构; n型源极层，其具有经由栅绝缘膜的一部分位于与栅电极相对的位置的上表面; 位于与n型源极相邻的栅电极的相对位置并且经由栅极绝缘膜的另一部分的p型基极层; n型半导体层，其与栅极绝缘膜的另一部分位于与栅极电极相对的位置，其与p型基极层相邻，而不与n型源极层接触; 以及p型接触层，其中至少两个峰位于比从与n型源极层接触的n型源极层的上表面的形成深度更浅的位置处，并且p 并且还具有构成与该n型源极层的上表面相同的平面的上表面，而杂质浓度值的轮廓从该上表面到深度方向具有至少两个峰。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006166562A Dc-dc converter 审中-公开
标题翻译： DC-DC转换器
公开(公告)号：JP2006166562A
公开(公告)日：2006-06-22
申请号：JP2004352921
申请日：2004-12-06
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAGUCHI YUSUKE , YAMAGUCHI YOSHIHIRO , ONO SHOTARO , NAKAMURA KAZUTOSHI , MATSUSHITA KENICHI
IPC分类号： H02M3/155
摘要： PROBLEM TO BE SOLVED: To reduce loss in a DC-DC converter that steps down a primary-side DC voltage, and outputs it as a secondary-side voltage.
SOLUTION: The DC-DC converter is provided with: a first MOSFET that comprises a first drain terminal that can be fed with the primary-side voltage, a first gate terminal that can be fed with a first control voltage, and a first source terminal that outputs a current flowing into the first drain terminal; a second MOSFET that comprises a second drain terminal that is connected to the first source terminal of the first MOSFET and serves as a secondary-side output node, a second gate terminal that can be fed with a second control voltage, and a second source terminal that can return a current flowing into the second drain terminal to the negative side of the primary-side voltage; and a series connecting element composed of an inductor and a shot-key diode whose second drain side serves as a cathode.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了减少降压初级侧直流电压的DC-DC转换器的损耗，并将其作为次级侧电压输出。解决方案：DC-DC转换器设置有：第一MOSFET，其包括可以馈送初级侧电压的第一漏极端子，可被馈送第一控制电压的第一栅极端子，以及第一源极端子，其输出流入第一漏极端子的电流; 第二MOSFET，其包括连接到第一MOSFET的第一源极端子并用作次级侧输出节点的第二漏极端子，可以馈送第二控制电压的第二栅极端子和第二源极端子可以将流入第二漏极端子的电流返回到初级侧电压的负侧; 以及由电感器和第二漏极侧用作阴极的击穿二极管组成的串联元件。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005096770A Power converter for rolling stock 审中-公开
标题翻译：电力转换器滚动库存
公开(公告)号：JP2005096770A
公开(公告)日：2005-04-14
申请号：JP2004370628
申请日：2004-12-22
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI YOSHIHIRO , YOSHINARI HIROAKI , HASHIMOTO TAKASHI
IPC分类号： B61C17/12 , B61C17/00 , H05K7/20
摘要： PROBLEM TO BE SOLVED: To provide a power converter for a rolling stock capable of realizing larger capacity and miniaturization/lightweight structure and maintenance/labor-saving in examination, and ready for higher speeding up of a train.
SOLUTION: The power converter for the rolling stock comprises a box body 2 suspended from a floor of the rolling stock, an air inlet 2b formed in one side of the box body 2 in the rail direction, an auxiliary air inlet 2e provided in the box body 2, an air outlet 2c formed in one side of the box body 2 in the sleeper direction, a wind tunnel 6 to communicate the air inlet 2b with the air outlet 2c with cooled air from the air inlet 2b flowing therein, a semi-conductor unit 7 having a heat radiation unit protruded and stored in the wind tunnel 6 on the air inlet 2b side, reactors 8A and 8B stored in the box body 2, and electric fans 9A and 9B to guide the cooled air from the air inlet 2b and the auxiliary air inlet 2e into the reactors 8A and 8B.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够实现更大容量和小型化/轻量化结构以及检查中的维护/省力的用于车辆的动力转换器，并且准备更高速度的列车。解决方案：用于车辆的动力转换器包括从车辆的地板悬挂的箱体2，沿轨道方向形成在箱体2的一侧的空气入口2b，设置有辅助空气入口2e 在箱主体2中，形成在箱体2的轨枕方向的一侧的空气出口2c，将空气入口2b与空气出口2c连通的风洞6与来自其中的空气入口2b的冷却空气连通，具有散热单元的半导体单元7，其突出并存储在空气入口2b侧的风洞6中，存储在箱体2中的电抗器8A和8B，以及电风扇9A和9B，用于将冷却的空气从空气入口2b和辅助空气入口2e进入电抗器8A和8B。版权所有（C）2005，JPO＆NCIPI

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