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1. 发明专利

JP2015053400A 半導体装置有权
标题翻译：半导体器件
公开(公告)号：JP2015053400A
公开(公告)日：2015-03-19
申请号：JP2013185612
申请日：2013-09-06
申请人：株式会社東芝 , Toshiba Corp
发明人： HARA TAKUMA , NAKAMURA KAZUTOSHI , OGURA TSUNEO
IPC分类号： H01L29/739 , H01L29/78
CPC分类号： H01L29/7395 , H01L29/0834 , H01L29/1095 , H01L29/7397
摘要：【課題】バリア層を備える電力用トランジスタのターンオフ時のロスを低減する。【解決手段】一の実施形態によれば、半導体装置は、第1の面と、前記第1の面に対向する第2の面とを有する、第1導電型の第1半導体層と、前記第1半導体層の前記第1の面に形成された、第2導電型の第2半導体層とを備える。さらに、前記装置は、前記第1および第2半導体層に形成され、前記第1の面に平行な第1方向に延びている、複数の制御電極と、前記第2半導体層の前記第1半導体層とは反対側に、前記第1方向に沿って交互に形成された、前記第1導電型の複数の第3半導体層および前記第2導電型の複数の第4半導体層とを備える。さらに、前記装置は、前記第2半導体層の前記第1半導体層側、または前記第2半導体層に包囲される位置に形成された、前記第1導電型の複数の第5半導体層を備え、前記第5半導体層は、前記第1方向に沿って互いに離間して配置されている。【選択図】図1
摘要翻译：要解决的问题：减少在关断时包括阻挡层的功率晶体管的损耗。解决方案：一种半导体器件包括具有第一表面的第一导电型第一半导体层和面向第一表面的第二表面以及形成在第一半导体层的第一表面上的第二导电型第二半导体层。此外，该器件包括形成在第一和第二半导体层中并沿与第一表面平行的第一方向延伸的多个控制电极，以及多个第一导电型第三半导体层和多个第二导电型第三半导体层，在第二半导体层的与形成有第一半导体层的一侧相反的一侧沿着第一方向交替形成第四半导体层。此外，该器件包括形成在位于第二半导体层的第一半导体层侧的位置或由第二半导体层包围的位置的多个第一导电型第五半导体层。第五半导体层沿着第一方向彼此间隔开设置。

2. 发明专利

JP2014112637A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014112637A
公开(公告)日：2014-06-19
申请号：JP2013110390
申请日：2013-05-24
申请人： Toshiba Corp , 株式会社東芝
发明人： OGURA TSUNEO , MATSUDAI TOMOKO , OSHINO YUICHI , MISU SHINICHIRO , IKEDA YOSHIKO , NAKAMURA KAZUTOSHI
IPC分类号： H01L29/868 , H01L21/28 , H01L29/06 , H01L29/47 , H01L29/861 , H01L29/872
CPC分类号： H01L27/0814 , H01L29/083 , H01L29/45 , H01L29/47 , H01L29/66136 , H01L29/7391 , H01L29/861 , H01L29/868 , H01L29/87
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a high breakdown voltage.SOLUTION: The semiconductor device comprises: a first electrode; a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, having a lower impurity concentration than that of the first semiconductor layer; a first semiconductor region of a second conductivity type, provided on a part of the second semiconductor layer; a second semiconductor region of the second conductivity type, being in contact with the first semiconductor region; a third semiconductor region of the second conductivity type, provided on a part of the first semiconductor region; and a second electrode provided on the first semiconductor region, the second semiconductor region, and the third semiconductor region. The impurity concentration in a surface in contact with the second electrode in the third semiconductor region is higher than that in the first semiconductor region and that in a surface in contact with the second electrode in the second semiconductor region. The thickness of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer is thinner than the thickness of the second semiconductor layer sandwiched between the second semiconductor region and the first semiconductor layer.
摘要翻译：要解决的问题：提供具有高击穿电压的半导体器件。解决方案：半导体器件包括：第一电极; 第一导电类型的第一半导体层; 具有比第一半导体层的杂质浓度低的第一导电类型的第二半导体层; 设置在所述第二半导体层的一部分上的第二导电类型的第一半导体区域; 第二导电类型的第二半导体区域与第一半导体区域接触; 设置在第一半导体区域的一部分上的第二导电类型的第三半导体区域; 以及设置在第一半导体区域，第二半导体区域和第三半导体区域上的第二电极。在第三半导体区域中与第二电极接触的表面中的杂质浓度高于第一半导体区域中的杂质浓度，并且在第二半导体区域中与第二电极接触的表面中的杂质浓度高。夹在第一半导体区域和第一半导体层之间的第二半导体层的厚度比夹在第二半导体区域和第一半导体层之间的第二半导体层的厚度薄。

3. 发明专利

JP2014078689A Power semiconductor device and method of manufacturing the same 审中-公开
标题翻译：功率半导体器件及其制造方法
公开(公告)号：JP2014078689A
公开(公告)日：2014-05-01
申请号：JP2013146968
申请日：2013-07-12
申请人： Toshiba Corp , 株式会社東芝
发明人： OSHINO YUICHI , SUESHIRO TOMOKO , NAKAMURA KAZUTOSHI , MISU SHINICHIRO , HARA TAKUMA
IPC分类号： H01L29/78 , H01L21/329 , H01L21/336 , H01L27/04 , H01L29/06 , H01L29/739 , H01L29/861 , H01L29/868
CPC分类号： H01L29/7393 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0638 , H01L29/0653 , H01L29/0661 , H01L29/404 , H01L29/66325 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a power semiconductor device capable of facilitating miniaturization.SOLUTION: In the method of manufacturing the power semiconductor device, an upper part of a semiconductor substrate in a terminal region, an upper surface of a first diffusion layer, and an upper surface of a first oxide film are etched so that the position of the upper surface of the semiconductor substrate in the terminal region, including the first oxide film and the first diffusion layer, is lower than the upper surface of the semiconductor substrate in a cell region. Then, a second oxide film is formed on the semiconductor substrate. An embedded electrode is formed on the second oxide film from a first region to the side of the cell region over the first diffusion layer so that the position of the upper surface of the embedded electrode is lower than the upper surface of the semiconductor substrate in the cell region.
摘要翻译：要解决的问题：提供一种制造能够促进小型化的功率半导体器件的方法。解决方案：在制造功率半导体器件的方法中，在端子区域中的半导体衬底的上部，第一扩散层和第一氧化物膜的上表面被蚀刻，使得包括第一氧化物膜和第一扩散层的端子区域中的半导体衬底的上表面的位置低于第一氧化膜的上表面半导体衬底。然后，在半导体衬底上形成第二氧化膜。在第一扩散层上，从第一区域到第二扩散层的单元区域侧的第二氧化膜上形成嵌入电极，使得嵌入电极的上表面的位置比半导体衬底的上表面低细胞区域。

4. 发明专利

JP2014060336A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014060336A
公开(公告)日：2014-04-03
申请号：JP2012205741
申请日：2012-09-19
申请人： Toshiba Corp , 株式会社東芝
发明人： OGURA TSUNEO , NAKAMURA KAZUTOSHI , NINOMIYA HIDEAKI , SUESHIRO TOMOKO , OSHINO YUICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/739
CPC分类号： H01L29/7395 , H01L29/0696 , H01L29/1095 , H01L29/4236 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a power transistor capable of attaining both miniaturization and high performance.SOLUTION: A semiconductor device includes: a semiconductor substrate having first and second primary surfaces; a plurality of control electrodes formed in grooves formed in the first primary surface of the semiconductor substrate and extending in a first direction parallel to the first primary surface; and a plurality of control wiring lines formed on the first primary surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. Moreover, the semiconductor substrate includes a first semiconductor layer of a first conductivity type, and one of more second semiconductor layers of a second conductivity type formed on a surface of the first semiconductor layer on the first primary surface side. Further, the semiconductor substrate includes one or more third semiconductor layers of the first conductivity type formed in a surface of the second semiconductor layer on the first primary surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type formed on the second primary surface of the semiconductor substrate.
摘要翻译：要解决的问题：提供一种具有能够实现小型化和高性能的功率晶体管的半导体器件。解决方案：半导体器件包括：具有第一和第二主表面的半导体衬底; 形成在所述半导体衬底的所述第一主表面中并沿平行于所述第一主表面的第一方向延伸的凹槽中的多个控制电极; 以及多个控制布线，其形成在所述半导体基板的所述第一主表面上并且沿与所述第一方向垂直的第二方向延伸。此外，半导体衬底包括第一导电类型的第一半导体层和形成在第一主表面侧上的第一半导体层的表面上的第二导电类型的更多的第二半导体层之一。此外，半导体衬底包括一个或多个第一导电类型的第三半导体层，形成在第一主表面侧的第二半导体层的表面上并在第二方向上延伸，并且形成第二导电类型的第四半导体层在半导体衬底的第二主表面上。

5. 发明专利

JP2013084992A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013084992A
公开(公告)日：2013-05-09
申请号：JP2013008265
申请日：2013-01-21
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA KAZUTOSHI , YASUHARA NORIO
IPC分类号： H01L27/06 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in reliability.SOLUTION: According to an embodiment, a semiconductor device comprises a first switching element connected between an input voltage line and an inductive load, and a second switching element parallel-connected between an inductive load and a reference voltage line. The relationship is represented as 0
摘要翻译：要解决的问题：提供可靠性优异的半导体器件。解决方案：根据实施例，半导体器件包括连接在输入电压线和感性负载之间的第一开关元件和并联连接在感性负载和参考电压线之间的第二开关元件。该关系表示为0 <（第二开关元件的阈值电压）<（第二开关元件的内置二极管的导通状态电压）。在第二开关元件的栅极电压为基准电位的情况下，当第一开关元件与第二开关元件之间的节点的电位变得大于 - （第二开关元件的阈值电压）时，第二开关元件截止开关元件），并且当节点的电位变得小于 - （第二开关元件的阈值电压）时，第二开关元件导通。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2010010459A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010010459A
公开(公告)日：2010-01-14
申请号：JP2008168790
申请日：2008-06-27
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDAI TOMOKO , YASUHARA NORIO , NAKAMURA KAZUTOSHI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a short channel can be attained without shortening the gate length of a gate electrode itself.
SOLUTION: In this semiconductor device, the end part on the gate electrode 4 side in a drift region 8 extends to the underneath of the gate electrode 4, and when the gate length of the gate electrode 4 is denoted by Lg, and the length of the portion 8a underneath the gate electrode 4 in the drift region 8 is denoted by Ld, Ld
摘要翻译：要解决的问题：提供一种半导体器件，其中可以获得短沟道而不缩短栅极本身的栅极长度。解决方案：在该半导体器件中，漂移区8中的栅电极4侧的端部延伸到栅电极4的下方，并且当栅电极4的栅极长度由Lg表示时，以及漂移区8中的栅电极4下方的部分8a的长度由Ld表示，Ld

7. 发明专利

JP2009272415A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009272415A
公开(公告)日：2009-11-19
申请号：JP2008120943
申请日：2008-05-07
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUHARA NORIO , NAKAMURA KAZUTOSHI , NAKA TOSHIYUKI
IPC分类号： H01L21/8238 , H01L27/092 , H02M1/08 , H02M3/155
摘要： PROBLEM TO BE SOLVED: To provide a DC-DC converter which has small current loss accompanying switching.
SOLUTION: In the DC-DC converter 1, a high-side power transistor Q1 and a low-side power transistor Q2 are connected in series between high-potential power wiring PH and low-potential power wiring PL. Further, an LC filter 15 is connected between a connection point LX and an output terminal Tout. Then the range of a potential applied to the gate of the high-side power transistor Q1 and the range of a potential applied to the gate of the low-side power transistor Q2 are set inside the range (Vin1 to GND) between potentials applied to both ends of a circuit comprising the high-side power transistor Q1 and low-side power transistor Q2.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供伴随切换具有小电流损耗的DC-DC转换器。解决方案：在DC-DC转换器1中，高边功率晶体管Q1和低侧功率晶体管Q2串联连接在高电位电源配线PH和低电位电力线PL之间。此外，LC滤波器15连接在连接点LX和输出端子Tout之间。然后，施加到高侧功率晶体管Q1的栅极的电位的范围和施加到低侧功率晶体管Q2的栅极的电位的范围被设定在施加到低功率晶体管Q1的电位之间的范围（Vin1〜GND）内包括高侧功率晶体管Q1和低侧功率晶体管Q2的电路的两端。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2008140824A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008140824A
公开(公告)日：2008-06-19
申请号：JP2006323136
申请日：2006-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA KAZUTOSHI
IPC分类号： H01L27/08 , H01L21/822 , H01L27/04 , H02M3/155
CPC分类号： H01L27/088 , H01L21/763 , H01L21/823481
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing erroneous operations by suppressing a current flowing into peripheral circuits of a power transistor, while increase in a chip area is not permitted.
SOLUTION: The semiconductor device is constituted to include a P-type semiconductor substrate 1, a P-type well layer 2 selectively formed on the P-type semiconductor substrate 1, a N
+ -type source layer 5 selectively formed on the P-type well layer 2, a N
+ -type drain layer 6 (N-type field moderating layer 7) formed on the P-type well layer 2 and separated from the N
+ -type source layer 5, a gate electrode 17 formed between the N
+ -type source layer 5 and the N
+ -type drain layer 6 via an insulating layer 16, a first trench 4 formed by surrounding the P-type well layer 2, namely by digging down the P-type semiconductor substrate 1 between the P-type well layer 2 and the N-type well layer 3, and a N
+ -type diffusing layer 12 formed within the first trench 4, in order to set the P-type source layer 5 and the N-type diffusing layer 12 in the equal electrical potential.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，用于通过抑制流入功率晶体管的外围电路的电流来防止误操作，而不允许增加芯片面积。解决方案：半导体器件被构造为包括P型半导体衬底1，P型阱层2，P型阱层2选择性地形成在P型半导体衬底1上，N + 型源极层5选择性地形成在P型阱层2上，形成在P型阱层2上的N + SP +型漏极层6（N型场缓和层7）形成在N + 型源极层5之间的栅极电极17和N + SP + 漏极层6，通过围绕P型阱层2形成的第一沟槽4，即通过挖掘P型阱层2和N型阱层之间的P型半导体衬底1而形成 3，以及形成在第一沟槽4内的N + 型扩散层12，以便将P型源极层5和N型漫射层12设置在等电位。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2005116876A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005116876A
公开(公告)日：2005-04-28
申请号：JP2003350819
申请日：2003-10-09
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHIRO TOMOKO , NAKAMURA KAZUTOSHI , NAKAGAWA AKIO
IPC分类号： H01L29/872 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L29/47 , H01L29/76
CPC分类号： H01L27/0727
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a chip area and reducing the parasitic inductance of wiring.
SOLUTION: The semiconductor device comprises a p-type layer 13 formed on a p-type semiconductor substrate 11; a source region 14 formed in the surface region of the p-type layer 13; a drain region 15 formed separately from the source region 14; a reduced surface field layer 16 of a low density formed in the surface region of the p-type layer 13 between the source region 14 and the drain region 15 so as to be in contact with the drain region 15; a gate insulating film 17 formed on the p-type layer 13 between the source region 14 and the reduced surface field layer 16; a gate electrode 18 formed on the gate insulating film 17; a drain region 22 formed separately in a direction opposite to the gate electrode 18 from the drain region 15; and a Shottky electrode 23 formed on the p-type layer 13 between the drain region 15 and the drain region 22.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够减小芯片面积并降低布线的寄生电感的半导体器件。解决方案：半导体器件包括形成在p型半导体衬底11上的p型层13; 形成在p型层13的表面区域中的源极区域14; 与源极区域14分开形成的漏极区域15; 形成在源极区域14和漏极区域15之间的p型层13的表面区域中以与漏极区域15接触的低密度的还原表面场层16; 形成在源极区域14和还原表面场层16之间的p型层13上的栅极绝缘膜17; 形成在栅极绝缘膜17上的栅电极18; 在与漏极区域15相反的方向上形成的漏极区域22; 以及形成在漏极区域15和漏极区域22之间的p型层13上的肖特基电极23.（C）2005，JPO＆NCIPI

10. 发明专利

JP2004253454A Semiconductor device 有权
公开(公告)号：JP2004253454A
公开(公告)日：2004-09-09
申请号：JP2003039765
申请日：2003-02-18
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA KAZUTOSHI , SUESHIRO TOMOKO , KAWAGUCHI YUSUKE , NAKAGAWA AKIO
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1083 , H01L29/7801
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a reactive current is reduced and substrate current is restrained. SOLUTION: The semiconductor device comprises a semiconductor substrate 110 having a main surface, a p-type semiconductor layer 130 arranged on the main surface of the semiconductor substrate 110; a p-type buried layer 140 arranged between the semiconductor layer 130 and the semiconductor substrate 110; a p-type first connection region 160 which is arranged in the ambients of the semiconductor layer 130 and reaches the buried layer 140 from a surface of the semiconductor layer 130; a switching element 10 arranged on the surface of the semiconductor layer 130; and a low breakdown voltage element 20 which is arranged on the surface of the semiconductor layer 130 which surface is positioned nearer to the connection region 160 than the switching element 10, and whose breakdown voltage is lower than that of the switching element 10. COPYRIGHT: (C)2004,JPO&NCIPI

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