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1. 发明专利

JP2013232263A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2013232263A
公开(公告)日：2013-11-14
申请号：JP2012104008
申请日：2012-04-27
申请人： Toshiba Corp , 株式会社東芝
发明人： MICHIOKA YOSHIHISA , ABE MITSUHIRO , WATANABE TOSHIFUMI , HAYASHI SHINTARO , OTA HITOSHI
IPC分类号： G11C29/42 , G06F12/16 , G11C16/04 , G11C16/06
CPC分类号： G11C7/1006 , G06F11/1048
摘要： PROBLEM TO BE SOLVED: To provide an architecture that achieves simplification of semiconductor memory operation.SOLUTION: A semiconductor memory of an embodiment includes: a buffer circuit 12 for input/output of data to a memory cell array; a data transfer circuit 17 that is connected to the buffer circuit 12 via a data bus IOBUS and transfers data of a first or second bit width; and an ECC circuit 20 that is connected to a data bus IOBUS and performs ECC processing for data of the second bit width. The buffer circuit 12 includes a pipe circuit 125 that inputs/outputs data of the first bit width. The data transfer circuit 17 includes: a data storage unit 171 that includes a plurality of latch circuits 71A and 71B holding the data of the first bit width and a selection circuit selecting one of the latch circuits 71A and 71B; and a data storage unit 172 that is connected to the ECC circuit 20 and holds the data of the second bit width.
摘要翻译：要解决的问题：提供实现半导体存储器操作简化的架构。解决方案：实施例的半导体存储器包括：用于向存储单元阵列输入/输出数据的缓冲电路12; 数据传输电路17，经由数据总线IOBUS连接到缓冲电路12，并传送第一或第二位宽的数据; 以及连接到数据总线IOBUS并对第二位宽度的数据进行ECC处理的ECC电路20。缓冲电路12包括输入/输出第一位宽度的数据的管电路125。数据传输电路17包括：数据存储单元171，其包括保持第一位宽度的数据的多个锁存电路71A和71B以及选择一个锁存电路71A和71B的选择电路; 以及连接到ECC电路20并保持第二位宽度的数据的数据存储单元172。

2. 发明专利

JP2012128922A Semiconductor memory device and method of testing the same 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：JP2012128922A
公开(公告)日：2012-07-05
申请号：JP2010281384
申请日：2010-12-17
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE TOSHIFUMI , ABE MITSUHIRO , ISHIZUKA KENJI
IPC分类号： G11C29/12
CPC分类号： G11C11/005 , G11C16/00 , G11C16/0483 , G11C29/44 , G11C29/702
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which facilitates identifying a failure spot.SOLUTION: A semiconductor memory device 1 includes first and second memories 2, 20, a data path between the first and second memories 2, 20, a register 51 for storing first data transferred in a first direction on the data path, and a comparison circuit 50 for comparing second data transferred in a second direction on the data path with the first data stored in the register 51 to detect a failure spot.
摘要翻译：要解决的问题：提供一种便于识别故障点的半导体存储器件。解决方案：半导体存储器件1包括第一和第二存储器2，20，第一和第二存储器2,20之间的数据路径，用于存储在数据路径上沿第一方向传送的第一数据的寄存器51，以及比较电路50，用于将数据路径上沿第二方向传送的第二数据与存储在寄存器51中的第一数据进行比较，以检测故障点。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2009059452A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2009059452A
公开(公告)日：2009-03-19
申请号：JP2007228248
申请日：2007-09-03
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： ISHIGURO SHIGEFUMI , WATANABE TOSHIFUMI
IPC分类号： G11C11/406 , G11C11/403
摘要： PROBLEM TO BE SOLVED: To widen a margin of an address setup in self-refresh operation and to increase burst access speed in an external refresh operation, in a pseudo SRAM having a self-refresh function.
SOLUTION: The semiconductor memory device comprises: a memory section requiring the refresh cycle operation for holding data stored in a plurality of memory cells 24a and 24b; a first clock transition detector circuit 15 for generating a trigger signal bCLKTD for burst operation; a bank address selector circuit 20 for controlling timing to fetch addresses; and a refresh detector circuit 16 for switching the timing to fetch addresses in the bank address selector circuit 20.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在具有自刷新功能的伪SRAM中，扩展自刷新操作中的地址设置的余量并增加外部刷新操作中的突发存取速度。解决方案：半导体存储器件包括：存储器部分，其需要用于保存存储在多个存储器单元24a和24b中的数据的刷新周期操作; 用于产生用于脉冲串操作的触发信号bCLKTD的第一时钟转换检测器电路15; 用于控制取出地址的定时的存储体地址选择电路20; 以及刷新检测器电路16，用于切换提取地址选择器电路20中的地址的定时。（C）版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2009059419A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009059419A
公开(公告)日：2009-03-19
申请号：JP2007225890
申请日：2007-08-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI
IPC分类号： G11C11/4091 , G11C11/403
摘要： PROBLEM TO BE SOLVED: To accelerate a core access of a pseudo SRAM.
SOLUTION: On a synchronizing mode, for instance, a precharge operation in a core section of a memory device 11 according to a control circuit 12 of the memory device is executed in accordance with a rise of chip enable signal/CE1. When there is no demand of a self refresh operation, a read operation with respect to the memory device 11 according to the control circuit 12 of the memory device is executed in accordance with an initial rise of a clock CLK after a fall of an address fetch signal/ADV, without performing the precharge operation before core access.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：加速伪SRAM的核心访问。解决方案：在同步模式下，例如，根据存储器件的控制电路12的存储器件11的核心部分中的预充电操作根据芯片使能信号/ CE1的上升来执行。当不需要自刷新操作时，根据存储器件的控制电路12的存储器件11的读取操作根据在地址提取下降之后的时钟CLK的初始上升来执行信号/ ADV，在核心访问之前不执行预充电操作。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2011023084A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011023084A
公开(公告)日：2011-02-03
申请号：JP2009169254
申请日：2009-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： HAMANO TOMOYUKI , ISHIGURO SHIGEFUMI , WATANABE TOSHIFUMI , UEHARA KAZUTO
IPC分类号： G11C11/41
CPC分类号： G11C8/04 , G11C11/41 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which attains high-frequency operation and high speed.
SOLUTION: The semiconductor memory device includes: an SRAM core 47 having a plurality of memory cells; an address counter 41a incrementing addresses including a row address and a column address in synchronization with clock, and outputting the incremented addresses sequentially; a counter address detecting circuit 42a detecting an address before the row address is switched in an address output from the address counter 41a and outputting the detected signal; and an equalization control circuit 46a performing pre-charge operation for a bit line connected to a memory cell in accordance with a detected signal output from the counter address detecting circuit 42a.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现高频操作和高速度的半导体存储器件。解决方案：半导体存储器件包括：具有多个存储单元的SRAM核心47; 地址计数器41a与时钟同步地增加包括行地址和列地址的地址，并顺序地输出递增地址; 计数器地址检测电路42a检测在从地址计数器41a输出的地址中切换行地址之前的地址并输出检测到的信号; 以及均衡控制电路46a，根据从计数器地址检测电路42a输出的检测信号，对连接到存储单元的位线执行预充电操作。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010009646A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010009646A
公开(公告)日：2010-01-14
申请号：JP2008165012
申请日：2008-06-24
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： UEHARA KAZUTO , WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI , MURAOKA KAZUYOSHI
IPC分类号： G11C11/413 , G11C11/41 , G11C16/02 , G11C16/04
CPC分类号： G11C7/1027 , G11C7/1006 , G11C7/1039 , G11C11/005 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To increase a speed of a clock frequency in a semiconductor memory device configured to perform a clock synchronous burst read operation. SOLUTION: When a buffer memory 21a constituted of one bank is determined as a read target to execute the clock synchronous burst read operation and a start address STADD is a last column address, a burst read control circuit 41 starts counting up a SRAM address MEMADD in a cycle (a first clock) before reaching a read latency cycle (a fourth clock), and latches first read data D3 of a first word to the data latch (A) 281. A row address is switched to start reading of read data D4 of a second word. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高配置为执行时钟同步突发读取操作的半导体存储器件中的时钟频率的速度。解决方案：当将由一个组成的缓冲存储器21a确定为读取目标以执行时钟同步突发读取操作，并且起始地址STADD是最后一个列地址时，突发读取控制电路41开始计数SRAM 在达到读延迟周期（第四时钟）之前以一个周期（第一时钟）寻址MEMADD，并将第一个字的第一读取数据D3锁存到数据锁存器（A）281。行地址被切换以开始读取读取第二个字的数据D4。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2008108404A Integrated semiconductor circuit 审中-公开
标题翻译：集成半导体电路
公开(公告)号：JP2008108404A
公开(公告)日：2008-05-08
申请号：JP2006292954
申请日：2006-10-27
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： WATANABE TOSHIFUMI , MARUYAMA KEIJI
IPC分类号： G11C11/4091
摘要： PROBLEM TO BE SOLVED: To provide an integrated semiconductor circuit which can reduce the power consumption even when using transistors connecting memory cells and sense amplifiers.
SOLUTION: The operation of the control signal A is stopped when column operations are not needed in the integrated semiconductor circuit operating the control signal A of the transistors connecting memory cells and sense amplifiers during access.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供即使在连接存储单元和感测放大器的晶体管时也能降低功耗的集成半导体电路。解决方案：在连接存储单元和读出放大器的晶体管的控制信号A的集成半导体电路中不需要列操作时，停止控制信号A的操作。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2012119033A Memory system 审中-公开
标题翻译：记忆系统
公开(公告)号：JP2012119033A
公开(公告)日：2012-06-21
申请号：JP2010267828
申请日：2010-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KASHIWAGI HITOSHI , FUJITA SHIRO , WATANABE TOSHIFUMI
IPC分类号： G11C11/413
CPC分类号： G11C16/0483 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To provide a memory system capable of reading data out fast.SOLUTION: The memory system includes: a plurality of banks each having a memory cell array and a sense amplifier; a buffer circuit electrically connected to the banks through a data bus; a switch circuit which changes electric connections between the plurality of bank and the buffer circuit, an interface electrically connected to the buffer circuit; and a control part which controls the banks, buffer circuit, switch circuit, and interface. When data held in the memory cell array is output to the interface with five clocks, the control part controls the switch circuit to electrically connect the banks and the buffer circuit after the clocks are input to the banks and 1.5 clocks elapses, and outputs the data read out of the banks to a burst buffer.
摘要翻译：要解决的问题：提供能够快速读取数据的存储器系统。存储器系统包括：多个存储体，每个存储体具有存储单元阵列和读出放大器; 缓冲电路，通过数据总线电连接到组; 改变多个存储体和缓冲电路之间的电连接的开关电路，电连接到缓冲电路的接口; 以及控制部件，缓冲电路，开关电路和接口的控制部件。当保存在存储单元阵列中的数据以五个时钟输出到接口时，控制部分控制开关电路在时钟被输入到存储体之后电连接存储体和缓冲电路，并经过1.5个时钟，并输出数据从银行读出一个突发缓冲区。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011023085A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011023085A
公开(公告)日：2011-02-03
申请号：JP2009169255
申请日：2009-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI , HAMANO TOMOYUKI , UEHARA KAZUTO
IPC分类号： G11C11/41
CPC分类号： G11C7/12 , G11C8/12 , G11C11/005
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which increases the speed of synchronization. SOLUTION: The semiconductor memory device has a BootRAM having a first number of banks, DataRAM having a second number of banks which is larger than the first number of banks, and an equalizing timer control circuit 42 that controls pre-charge operation performed for a bit line provided at the BootRAM and the DataRAM. When the BootRAM is synchronized with clock, the equalizing timer control circuit 42 changes an operation time for a second pre-charge operation different from that for a first pre-charge operation after receiving an address ADD, between completion of an initial first pre-charge operation and start of the next second pre-charge operation. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种增加同步速度的半导体存储器件。解决方案：半导体存储器件具有具有第一数量的存储体的BootRAM，DataRAM具有大于第一数量的存储体的第二数量的存储体;以及均衡定时器控制电路42，其控制执行的预充电操作对于BootRAM和DataRAM提供的位线。当BootRAM与时钟同步时，均衡定时器控制电路42在接收到地址ADD之后，在完成初始的第一预充电之后，改变与第一预充电操作不同的第二预充电操作的操作时间操作和开始下一个第二次预充电操作。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2008021340A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008021340A
公开(公告)日：2008-01-31
申请号：JP2006189695
申请日：2006-07-10
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI
IPC分类号： G11C11/4076 , G11C11/403 , G11C11/407
CPC分类号： H03K19/017509 , H03K5/19
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption when synchronizing in a semiconductor device which guarantees both a synchronous operation and an asynchronous operation. SOLUTION: The semiconductor memory is capable of carrying out a synchronous operation to take in signals inputted from the outside by synchronizing with the clock and an asynchronous operation to take in the input signals without synchronizing with the clock. It has an input terminal to supply the signals, a delay circuit connected to the input terminal and having an input and output, an input detecting circuit to detect the transition of the input signals and to generate pulse signals according to their transitions, and a control circuit to generate control signals different from one another depending on whether it is in the synchronous operation or in the asynchronous operation. It stops the operation of the input detecting circuit by the control signals. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了在保证同步操作和异步操作的半导体器件中同步时降低功耗。解决方案：半导体存储器能够执行同步操作，以通过与时钟同步来接收从外部输入的信号和异步操作以接收输入信号而不与时钟同步。它具有输入端以提供信号，连接到输入端并具有输入和输出的延迟电路，输入检测电路，用于检测输入信号的转变并根据其转变产生脉冲信号;以及控制电路，以根据其是处于同步操作还是异步操作来产生彼此不同的控制信号。它通过控制信号停止输入检测电路的工作。版权所有（C）2008，JPO＆INPIT

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